prismprojection

Clock

12 posts in this topic

Can I gain access to the 32Mhz clock without using the ZPUino core? I added the "CLK" net marker from the utility schematic, but when I try to simulate the circuit in ISE the "CLK" line isn't oscillating. 

I've attached my schematic. I'm trying to make a 20-bit PWM. Ultimately the constant value will be from GPIO pins.

Thanks.

20-bit PWM.png

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In simulation there needs to be a "test bench" that your circuit plugs into.  The test bench drives the clk signal with a 32 MHz square wave.  In other words, you need to generate the 32 MHz clock signal in simulation.  In real life it's driven by the oscillator on the board.

Magnus

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So, I'm still struggling with this.

I added this source file to the simulation, but I'm unclear how to connect "clk_200" to my schematic. (I removed the clk_32to288_dcm symbol and renamed the net to clk_200, but I guess ISE doesn't know they are connected)

-- TestBench Template 

  LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.numeric_std.ALL;

entity tb is
end entity;

architecture sim of tb is

  -- Procedure for clock generation
  procedure clk_gen(signal clk : out std_logic; constant FREQ : real) is
    constant PERIOD    : time := 1 sec / FREQ;        -- Full period
    constant HIGH_TIME : time := PERIOD / 2;          -- High time
    constant LOW_TIME  : time := PERIOD - HIGH_TIME;  -- Low time; always >= HIGH_TIME
  begin
    -- Check the arguments
    assert (HIGH_TIME /= 0 fs) report "clk_plain: High time is zero; time resolution to large for frequency" severity FAILURE;
    -- Generate a clock cycle
    loop
      clk <= '1';
      wait for HIGH_TIME;
      clk <= '0';
      wait for LOW_TIME;
    end loop;
  end procedure;

  -- Clock frequency and signal
  signal clk_200 : std_logic;

begin

  -- Clock generation with concurrent procedure call
  clk_gen(clk_200, 200.000E6);  -- 200.000 MHz clock

  -- Time resolution show
  assert FALSE report "Time resolution: " & time'image(time'succ(0 fs)) severity NOTE;

end architecture;

 

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The schematic has been corrected and simulated. The next hurdle is I added "Papilio_Default_Pinout.vhd" to gain access to the boards GPIO for the PWM value and output, but I receive the following errors when I try to implement the top module.

ERROR:HDLParsers:3317 - "C:/DesignLab-1.0.7/libraries/Papilio_Hardware/Papilio_Default_Pinout.vhd" Line 23.  Library board cannot be found.
ERROR:HDLParsers:3013 - "C:/DesignLab-1.0.7/libraries/Papilio_Hardware/Papilio_Default_Pinout.vhd" Line 24. Library board is not declared.
Process "Synthesize - XST" failed

What can I do to resolve this? Thanks.

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I changed it to " Papilio_Default_Wing_Pinout" which removed the previously mentioned errors ... now the Mapping process clears all the logic. Is it that nothing is really connected to the IO pins? I thought adding the hardware symbol would allow access to the GPIO.

There isn't a soft core processor in this design.

error.png

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Hello prismprojection,

Looks like it was a busy weekend! Sorry I wasn't online to help answer your questions but it looks like you got things figured out. Is there any more outstanding questions?

Jack.

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Hi Jack,

No worries. I'll take a rain-check on answering more questions =)

I ordered the Papilio One 500K and LogicStart MegaWing today, and I'm very excited to start learning on actual hardware.

Thanks, Garrett

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I need help tracing down a warning and general improvements.

Here is the warning:

Signal <max_counter> is used but never assigned. This sourceless signal will be automatically connected to value 11111111111111111111

Here the VHDL code for a 20-bit PWM:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Generic_PWM_x1 is
port(
	clk: in std_logic;
	pwm_var: in std_logic_vector(19 downto 0);
	pwm_out: out std_logic
	
);
end Generic_PWM_x1;

architecture Behavioral of Generic_PWM_x1 is
signal counter: std_logic_vector(19 downto 0):= (others=>'0');
signal max_counter: std_logic_vector(19 downto 0):= (others=>'1');

begin

process(clk)
begin
	if rising_edge(clk) then
		counter <= std_logic_vector( unsigned(counter) + 1 );		
		if counter=max_counter then
			counter<=(others=>'0');
		else
			if counter<pwm_var then
				pwm_out<='1';
			else
				pwm_out<='0';
			end if;
		end if;
	end if;

end process;

end Behavioral;

It seems to me that it's assigned, so I need some guidance. In general, I'm also interested in improving the timing of this block, so any suggestions would be very much appreciated.

Thanks!

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max_counter has an initial value of all 1's but never assigned any other value so it's basically a constant.  The warning is just another way of saying that.

As for the timing of this block, I'm not sure what you are trying to accomplish here.  A 20 bit PWM circuit clocked at 200 MHz will have a period of about 200 Hz so you will need a very low frequency low-pass filter (~50 Hz) on the PWM output if you are trying to implement some sort of DAC.  In general, for PWM DACs and delta-sigma DACs, the more bits of resolution you have the lower frequency components will show up on the output.  Maybe your application is fine with a 50 Hz cut-off on the output, if not then I suggest rethinking your design.

I'm not sure this relates to your project but this thread might have useful information: http://forum.gadgetfactory.net/index.php?/topic/2378-cd-quality-audio-441khz-delta-sigma-dac-spartan-6/

Magnus

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