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Need little help to Implement this Virtual 7 Segment display on VGA

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Hi,

I'm trying to implement  Virtual 7 Segment display on VGA VHDL code on Nexys 3 board

this code implemented on Papilio One with Megawing Shield

http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/logicstart-megawing/virtual-7-segment-display-on-vga-r37


I change the VGA pinout in UCF file but there is something I don't understand it that Nexys 3 have 8 pins for VGA adapter

3 for green
3 for red
2 for blue
 

NET "rgb[7]" LOC = U7 | IOSTANDARD = LVCMOS33;NET "rgb[6]" LOC = V7 | IOSTANDARD = LVCMOS33;NET "rgb[5]" LOC = N7 | IOSTANDARD = LVCMOS33;NET "rgb[4]" LOC = P8 | IOSTANDARD = LVCMOS33;NET "rgb[3]" LOC = T6 | IOSTANDARD = LVCMOS33;NET "rgb[2]" LOC = V6 | IOSTANDARD = LVCMOS33;NET "rgb[1]" LOC = R7 | IOSTANDARD = LVCMOS33;NET "rgb[0]" LOC = T7 | IOSTANDARD = LVCMOS33;

While in the "Virtual 7 Segment display on VGA VHDL code" the author use only 1 pin for each color, Also mega wing schematic have the same thing there are primary pins VGA adapter and secondary pins (3 pins for green and red while blue got 2 pins)

I make some change in the code to make it work in Nexys 3 FPGA board like changing the Entity from

STD_LOGIC to STD_LOGIC_VECTOR (2 downto 0)

But I still get this error

ERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 88: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 89: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 90: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 91: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 92: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\Uvga7seg\source\seven_segment_top.vhd" Line 93: Indexed name is not a std_logic_vectorERROR:HDLCompiler:854 - "C:\vga7seg\source\seven_segment_top.vhd" Line 23: Unit <rtl> ignored due to previous errors.


 

vga7seg.zip

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I don't have the code you referenced but I am assuming it is displaying a seven segment on vga. Maybe you are trying to connect the virtual seven segment lines to the vga lines. I believe the errors you are getting are because you are attempting to connect a std_logic_vector to a std_logic signal. If you are trying to connect a one bit vga signal to a three bit you should probably connect the single bit to the msb of the multibit and set the non-msbs to zero.

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When it comes to VGA output, different boards will have different numbers of digital pins used to generate the analog color lines.  On Papilio the VGA Wing uses three (one per color component), the LogicStart MegaWing uses eight (2-3 per color component), and the Arcade MegaWing uses twelve (4 per color component).  So when adapting a design, meant for one of them, to another, you have to change the relevant parts.

 

As for the errors you're getting, I can't be much help, as I don't work usually with VHDL but with Verilog instead.  But what I suspect is that there's a difference between a single logic signal (STD_LOGIC) and an array of some number of logic signals (STD_LOGIC_VECTOR) even if the "some number" is 1.  I believe that's the same thing treadstone says above.  You might have to make small changes to the syntax of the VHDL code to change one to the other.

 

To up convert from one bit per component to three or four, you can do what treadstone suggests above (make that one bit the msb, and fill the rest in with zero) though what I'd usually do instead is copy that one bit to all three or four.

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I agree with Jaxartes that when going from one bit to multibit vectors connection of the single bit to all bits of the vector is a better solution, go from zero to full scale. Thanks for correcting that. If you want to go the other way from multibit to one bit you would use just the msbit of the vector as its transition from 0 to 1 represents the mid point. This is only on unsigned of course.

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thank, I believe your answer solve my problem but I'm newbie in FPGA and I use it for do very simple example in my home like connect button and try to implement some gate when the board receive signal the led turn on and something like this,

 

my problem is :D I don't know how to "make small changes to the syntax of the VHDL code" and don't understand what is that mean "you should probably connect the single bit to the msb of the multibit and set the non-msbs to zero.",

 

Al last thanks for helping I was thought it will be easy to write hello world by using FPGA connected to LCD via VGA.

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Look up concatenation in an hdl design book, that is what you are trying to do.

If you have a std_logic signal x and a 3 bit std_logic_vector y then you do this:

y <= x & x & x;

to copy the single bit x to each bit of the vector y.

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I deactivate this lines
 

begin    -- connect internal video signals to outputs    O_VIDEO_R <= VideoR;    O_VIDEO_G <= VideoG;    O_VIDEO_B <= VideoB;

and make this changes

begin    -- connect internal video signals to outputs    --O_VIDEO_R <= VideoR;    --O_VIDEO_G <= VideoG;    --O_VIDEO_B <= VideoB;    VideoR <= O_VIDEO_R[0] & O_VIDEO_R[1] & O_VIDEO_R[2];    VideoG <= O_VIDEO_G[0] & O_VIDEO_G[1] & O_VIDEO_G[2];    VideoB <= O_VIDEO_B[0] & O_VIDEO_B[1];

but still get this error

ERROR:HDLCompiler:806 - "C:\vga7seg\source\seven_segment_top.vhd" Line 46: Syntax error near "0".ERROR:HDLCompiler:806 - "C:\vga7seg\source\seven_segment_top.vhd" Line 47: Syntax error near "0".ERROR:HDLCompiler:806 - "C:\vga7seg\source\seven_segment_top.vhd" Line 48: Syntax error near "0".ERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 98: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 99: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 100: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 101: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 102: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 103: Indexed name is not a std_logic_vectorERROR:HDLCompiler:854 - "C:\vga7seg\source\seven_segment_top.vhd" Line 23: Unit <rtl> ignored due to previous errors

also I try to rewrite the line in difference way
 

begin      -- connect internal video signals to outputs      --O_VIDEO_R <= VideoR;      --O_VIDEO_G <= VideoG;      --O_VIDEO_B <= VideoB;      O_VIDEO_R <= VideoR[0] & VideoR[1] & VideoR[2];      O_VIDEO_G <= VideoG[0] & VideoG[1] & VideoG[2];      O_VIDEO_B <= VideoB[0] & VideoB[1];

and still get this error
 

ERROR:HDLCompiler:806 - "C:\vga7seg\source\seven_segment_top.vhd" Line 50: Syntax error near "0".ERROR:HDLCompiler:806 - "C:\vga7seg\source\seven_segment_top.vhd" Line 51: Syntax error near "0".ERROR:HDLCompiler:806 - "C:\vga7seg\source\seven_segment_top.vhd" Line 52: Syntax error near "0".ERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 97: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 98: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 99: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 100: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 101: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 102: Indexed name is not a std_logic_vectorERROR:HDLCompiler:854 - "C:\vga7seg\source\seven_segment_top.vhd" Line 23: Unit <rtl> ignored due to previous errors.



 

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with this change

begin	-- connect internal video signals to outputs	VideoR <= O_VIDEO_R(0) & O_VIDEO_R(1) & O_VIDEO_R(2);	VideoG <= O_VIDEO_G(0) & O_VIDEO_G(1) & O_VIDEO_G(2);	VideoB <= O_VIDEO_B(0) & O_VIDEO_B(1);

I get this :D

ERROR:HDLCompiler:288 - "C:\vga7seg\source\seven_segment_top.vhd" Line 46: Cannot read from 'out' object o_video_r ; use 'buffer' or 'inout'ERROR:HDLCompiler:288 - "C:\vga7seg\source\seven_segment_top.vhd" Line 47: Cannot read from 'out' object o_video_g ; use 'buffer' or 'inout'ERROR:HDLCompiler:288 - "C:\vga7seg\source\seven_segment_top.vhd" Line 48: Cannot read from 'out' object o_video_b ; use 'buffer' or 'inout'ERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 97: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 98: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 99: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 100: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 101: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 102: Indexed name is not a std_logic_vectorERROR:HDLCompiler:854 - "C:\vga7seg\source\seven_segment_top.vhd" Line 23: Unit <rtl> ignored due to previous errors.

and this change

begin	-- connect internal video signals to outputs	  O_VIDEO_R <= VideoR(0) & VideoR(1) & VideoR(2);	  O_VIDEO_G <= VideoG(0) & VideoG(1) & VideoG(2);	  O_VIDEO_B <= VideoB(0) & VideoB(1);

give me different errors (less errors :blink: )

ERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 97: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 98: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 99: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 100: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 101: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 102: Indexed name is not a std_logic_vectorERROR:HDLCompiler:854 - "C:\vga7seg\source\seven_segment_top.vhd" Line 23: Unit <rtl> ignored due to previous errors.

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You are doing several mistakes there.

 

Which are your internal signals, and which are your interface signals ? Can you post the whole VHDL file so we can understand ?

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I went to google code and looked at the original source your are trying to modify.  I don't know what other mods you made but from what I can see the errors you are getting above are caused by the fact that you didn't change the O_VIDEO_x signals into vectors.  You are also trying to connect the outputs to the internal signal in some cases, it only works the other way around.

 

Since the top level signals you are trying to make into 2 or 3 bit vectors are defined as std_logic right now if you want to make them 3 bit std_logic_vectors you need to do this:

 

change O_VIDEO_R : out std_logic; to O_VIDEO_R : out std_logic_vector(2 downto 0); in the entity definition (line 15 in the original code).  Do the same for the O_VIDEO_G and O_VIDEO_B, if you want them to be 2 bit instead of 3 then define them as std_logic_vector(1 downto 0);

 

then where the O_VIDEO_R is connected to the internal signal in the architecture (line 46 in the original code) connect it like this:

 

O_VIDEO_R <= VideoR & VideoR & VideoR;

 

Do the same thing for G and B.

 

The other thing you have to do is make changes in the constraints file to account for these extra bits.  The ucf files have the bits defined already you just need to comment out the original O_VIDEO_R (and G and B ) lines by inserting a pound sign in front of them (#) then remove the pound sign from the front of the lines that you want to connect, like O_VIDEO_R(2), O_VIDEO_R(1), O_VIDEO_R(0) and make sure all the signals are connected to the right pins on the FPGA. 

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His errors seem to come from a different part of the HDL, hence me asking for him to post the whole source.

 

Note the source lines in the error messages.

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The original source code got it from this link but there is some problem to download it so I suggest to download it from the attachment, I didn't make any change,
 
http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/logicstart-megawing/virtual-7-segment-display-on-vga-r37
 
Also I upload the UCF file for Nexys 3 board to make the code work on Nexys3

nexys3_master_ucf.zip

vga7seg-master.zip

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I think the same thing will happen with Papilio Pro if I want to Implement this code on it, Pro has also 3 Pins for Red, Green and 2 for Blue.

NET VGA_BLUE(0)    LOC="P92"  | IOSTANDARD=LVTTL;                                # B2NET VGA_BLUE(1)    LOC="P87"  | IOSTANDARD=LVTTL;                                # B3NET VGA_GREEN(0)   LOC="P84"  | IOSTANDARD=LVTTL;                                # B4NET VGA_GREEN(1)   LOC="P82"  | IOSTANDARD=LVTTL;                                # B5NET VGA_GREEN(2)   LOC="P80"  | IOSTANDARD=LVTTL;                                # B6NET VGA_RED(0)     LOC="P78"  | IOSTANDARD=LVTTL;                                # B7NET VGA_RED(1)     LOC="P74"  | IOSTANDARD=LVTTL;                                # B8NET VGA_RED(2)     LOC="P95"  | IOSTANDARD=LVTTL;                                # B9

Rhe source code for Nexys 3 board in the attachment,

vga7seg.zip

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I finally got to a computer and was able to download your original file and can see some of your problems.

 

1) You declare the VGA signals correctly in the top level entity on lines 15-17 as std_logic_vector but on lines 26-28 you need to keep VideoR, VideoG and VideoB as std_logic, not std_logic_vectors.  This will fix the errors that come up on lines 88, 90 and 93 during synthesis.  Change lines 26-28 to this:

 

signal VideoR     : std_logic;

signal VideoG     : std_logic;

signal VideoB     : std_logic;

 

2) On line 46 do connect the signal VideoR to each bit of the O_VIDEO_R like this:

 

O_VIDEO_R <= VideoR & VideoR & VideoR;

 

Do the same for the other two colors:

 

O_VIDEO_G <= VideoG & VideoG & VideoG;

O_VIDEO_B <= VideoB & VideoB; -- only 2 bits.

 

That should get you through synthesis. 

 

Now for the Place & Route, you need to make sure you have the correct signal names in the ucf file.  You need to uncomment (remove the leading #) and match the names to the names on your top level entity.  For example on the nexys3_master.ucf you need the change line 156 to:

 

NET O_VIDEO_R<0>         LOC = "U7"  | IOSTANDARD = "LVCMOS33";

 

do this for all the signals on your top level entity.

 

I think that will get you through all the problems I can see.

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I make the change

 

and this is my UCF file

## Clock signalNET "clk"            LOC = "V10" | IOSTANDARD = "LVCMOS33";   #Bank = 2, pin name = IO_L30N_GCLK0_USERCCLK,            Sch name = GCLKNet "clk" TNM_NET = sys_clk_pin;TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 25000 kHz;## VGA ConnectorNET O_VIDEO_R<0>         LOC = "U7"  | IOSTANDARD = "LVCMOS33";  NET O_VIDEO_R<1>         LOC = "V7"  | IOSTANDARD = "LVCMOS33";   NET O_VIDEO_R<2>         LOC = "N7"  | IOSTANDARD = "LVCMOS33";   NET O_VIDEO_G<0>         LOC = "P8"  | IOSTANDARD = "LVCMOS33";NET O_VIDEO_G<1>         LOC = "T6"  | IOSTANDARD = "LVCMOS33";NET O_VIDEO_G<2>         LOC = "V6"  | IOSTANDARD = "LVCMOS33";NET O_VIDEO_B<0>         LOC = "R7"  | IOSTANDARD = "LVCMOS33";NET O_VIDEO_B<1>         LOC = "T7"  | IOSTANDARD = "LVCMOS33";NET "Hsync"          LOC = "N6"  | IOSTANDARD = "LVCMOS33";                           NET "Vsync"          LOC = "P7"  | IOSTANDARD = "LVCMOS33";                          #NET "vgaRed<0>"      LOC = "U7"  | IOSTANDARD = "LVCMOS33";   # Bank = 2, Pin name = IO_L43P,                          Sch name = RED0#NET "vgaRed<1>"      LOC = "V7"  | IOSTANDARD = "LVCMOS33";   # Bank = 2, Pin name = IO_L43N,                          Sch name = RED1#NET "vgaRed<2>"      LOC = "N7"  | IOSTANDARD = "LVCMOS33";   # Bank = 2, Pin name = IO_L44P,                          Sch name = RED2#NET "vgaGreen<0>"    LOC = "P8"  | IOSTANDARD = "LVCMOS33";   # Bank = 2, Pin name = IO_L44N,                          Sch name = GRN0#NET "vgaGreen<1>"    LOC = "T6"  | IOSTANDARD = "LVCMOS33";   # Bank = 2, Pin name = IO_L45P,                          Sch name = GRN1#NET "vgaGreen<2>"    LOC = "V6"  | IOSTANDARD = "LVCMOS33";   # Bank = 2, Pin name = IO_L45N,                          Sch name = GRN2#NET "vgaBlue<1>"     LOC = "R7"  | IOSTANDARD = "LVCMOS33";   # Bank = 2, Pin name = IO_L46P,                          Sch name = BLU1#NET "vgaBlue<2>"     LOC = "T7"  | IOSTANDARD = "LVCMOS33";   # Bank = 2, Pin name = IO_L46N,                          Sch name = BLU2

I try both this like

TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 25000 kHz;

and nothing change, I got black screen everytime

 

so is there problem in adjusting the Clock Frequency or there is another way to write it?

 

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 I don't have a Nexsys 3 board but from the schematic the clock coming in on Pin V10 is a 100MHz clock.  You can't define it differently in the ucf, even if you do it will still be 100MHz.  You need to run it into a DCM and generate the appropriate clock, which looks like it needs to be 20MHz.  Use the IP manager in ISE or Vivado to do that, then instantiate it where it tells you to in the top level file (below line 52 in the original, it says -- use a DCM to generate 20Mhz clock required by VGA process)

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