Jack Gassett

Wishbone version of the Sump Blaze Logic Analyzer

10 posts in this topic

So Alvie and I have been talking and we want to work on a Wishbone version of the Sump Blaze Logic Analyzer core. The main benefits of this are:

  • The ability to use SRAM, SDRAM, or DDR ram through the Wishbone bus via DMA transfers. This will get us much more memory available for the Logic Analyzer.
  • It will be much easier to output the captured samples in different formats since it will be C code instead of VHDL code. It will be easy to add support for your favorite Logic Analyzer clients. Not only Jawi's OLS client but special modes for the Saleae client can be easily added as well.

So to get the ball rolling on this effort I've made a special version of the Sump Logic Analyzer core that has its control interface mapped to Wishbone bus registers. This version still uses internal BRAM but I've setup a simulation test bench to make the transition to DMA transfers for RAM easier to work out. The branch on github can be found here:

https://github.com/GadgetFactory/DesignLab_Examples/tree/Wishbone_Logic_Analyzer

 

The commit is:

https://github.com/GadgetFactory/DesignLab_Examples/commit/6019352579070f378304e9f710604b92e0f961cc

 

Or if you prefer a ready to go zip file:

Wishbone_Sump_LA.zip

 

Just open the Chip_Designer.xise file, change to simulation mode, and simulate the Simulate_Your_Chip_Design module as the top level.

 

The next step, moving to DMA memory, is something that's beyond my skills. :) Going to have to defer to Alvie's expertise for the next step, but am hoping to learn from the example of how DMA memory can be used with his new burst controller.

 

Jack.

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Here is a quick video of the simulation in action, let me do a quick written walkthrough:

 

  • How to open and access the simulation.
  • A look at the test bench where the wishbone commands to setup triggers, capture speed, etc are sent over the wishbone bus.
  • How to start the simulation.
  • A look at the decoder to see that it is capturing the correct setup commands from the wishbone bus.
  • A longer simulation time is added, it takes 80 micro seconds to see the entire write and read process.
  • A look at the point where the entire sampling is completed and the write signal goes to a read signal.
  • When this happens data is no longer captured and is instead sent out the serial port. 
  • The address counter reverses and counts down instead of up, we should see that the data that was captured at the last write clock is now being sent out when read is asserted.

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Wondering if you can simulate the latest version with the provided testbench :)

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Hey everyone,

 

Alvie and I just had an awesome breakthrough today on getting the Wishbone version of the Sump Logic Analyzer working so I recorded a video to show what we have working:

 

We still have more testing to do, bugs to fix, and things to figure out but this is a huge step in the direction of having a LOT more memory available for the Sump Logic Analyzer.

 

Jack.

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:)

And we were able to do a full simulation of the system, so we can find bugs on it.

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Hi Alvie and Jack,

 

this looks very interesting!

 

Jack, I believe you mentioned before that this project would contain a DMA module. Is this already implemented? If so, could you point out where it is so I can take a look at it?

 

Thanks

Stephan

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Hi Jack, Hi Alvie

 

This looks VERY interesting and could have saved me some work! Sounds like it could be exactly what I was looking for.

 

How would the data transfer to the computer be done? Serial line (USB)? Would this occupy the serial bus? Or could it run in parallel to serial debug output? (Does it use the "JTAG channel"?)

 

(Will this enhanced memory through DMA thingy also become available to other Logic Analyzer implementations as well? Or will this Wishbone Logic Analyzer be the recommended variant for future use?)

 

How can I upgrade by DesigLab setup in order to be able to use such a new library/code? Just clone it to the "libraries" folder? Anything else needed?

 

Sorry for asking that many questions at once. May be some are asked to early.

 

Thanks for this new library! Greetings.

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Jack and Alvie,

I would really like to try experiment with your Logic Analyzer implementation that uses DMA on a 2MB Duo.  In an earlier message you said you didn't have DMA working but could simulate it, and in a later message you seemed to suggest that DMA is working.  If I want to use your latest  version, where should I get it, and what works and what doesn't?  In your video, it is not using the OLS client, but instead is using an Zpuino program and the terminal.  Is this still the way it works?

Thanks,

Blake

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Well, I just tried to see if it works on the Papilio Pro and I didn't get a response using the OLS client. I only have about 15 minutes to put into it this morning unfortunately. Here is the latest version, you can unzip it into the libraries folder of your DesignLab installation and then find the Winsbone_Sump_LA/OLS_CLient example under Examples in DesignLab. You will then need to load the circuit to your board, load the sketch, and open the OLS client and try to connect to it. 

The status that we left off was that it was 80% working and just needed some bugs in the OLS_CLient sketch to be worked out...

Development fell off because we discovered that the performance is not that great. The best that we were seeing was about 30Ms/s...

Jack.

Wishbone_Sump_LA.zip

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