island_peter

upper and lower case in Linux

3 posts in this topic

Hi all,

 

I just wondered why my FPGA circuit is not loaded onto the board under Linux. So clicking the Load icon in DesignLab loads a bitfile down but it loads down an empty circuit from the template I guess..

When starting an new FPGA Circuit from DesignLab ISE will use capitalized filenames as e.g.

 

Papilio_One_500K.bit whereas DesignLab obviously tries to find a papilio_one_500k.bit all lower case. Simply renaming from upper to lowercase does the trick.

 

Just in case someone stumbled upon the same issue.

 

Cheers

Peter

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Thanks for pointing this out.  It happens to me too (with Papilio_Pro.bit / papilio_pro.bit).

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I have the same problem using Ubuntu with ISE 14.7 and a Papilio DUO.

For example, when I create a blank project in DesignLab, edit the circuit with ISE and then generate a bit file, ISE creates a file called "Papilio_DUO_LX9.bit". However, when I try to load the file with DesignLab, it looks for and loads "papilio_duo_lx9.bit" (lower case), which is the original blank project.

Cheers

Jon

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