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VDHL signal module question

5 posts in this topic

I had a VHDL question for any of the gurus out there. I am sure the issue is my mindset coming from a software background. Hopefully someone can set me straight.

 

I am trying to understand some Xilinx AXI bus code that seems to process the AXI registers in a submodule of the top module.

 

Say I have a top level module and another sub module that is instantiated from the top level module.

 

The sub module has ports for a bus and one or more registers. 

 

entity submod

port (

controlReg0 --Register to send control signals 

statusReg1 --register to return current operating status

bus --  multiple bus signals but just being high level here

);

Internally this sub module processes bus signals and stores register updates that come over the bus to the registers

 

In the top module

entity topmodule

port(

bus --multiple bus signals but just being high level here

);

 

Now within the top module code there are signals say reg0 and reg1 defined. Within the top module code it instantiates the submodule like so.

 

test : submod

port map (

reg0 => controlReg0,

reg1 => statusReg1,

bus=>bus

)

 

In this scenario are the reg0 in the top module and the controlReg0 in the submodule actually the same or are they 2 different actual entities. What I mean is when some data is sent over the bus and the value of controlReg0 is changed in the submodule is the value of reg0 also changed or do I need to do a specific assignment? And vice versa if the value of reg0 is changed in the top level module is that value reflected in the next read of the controlReg0 over the bus?

 

I think it looks like they are just 2 different references to the same register since in the port I set then to be the assigned to each other, but I could be way off here. Not sure how this is all handled once it is translated to hardware.

 

Any insight would be helpful.

 

Thanks,
Chris

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Unless you post the datatypes I cannot help you much.

Is controlReg0 a signal ? Is it a port input/output ? Is it a synchronous element ?

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Alvie,

Sorry I had left them off for brevity. Yes controlReg0 is defined as signal std_logic_vector(31 downto 0) in the top level module and reg0 is defined as signal std_logic_vector(31 downto 0) in the submodule. Basically the register size of the 32 bit bus.

 

The port is defined as OUT for reg0 and IN for reg1 on the submodule and I believe it is synchronous since both top level module and submodule processes are driven by the bus clock signal.

 

I would post the whole code but it was pretty large with pages of other logic around processing on the bus signals and all. I was just trying to simplify the example to just the specific area I was interested in understanding.

 

Any thoughts would be helpful.

 

Thanks,

Chris

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Hello Chris,

 

The answer to your question depends on some information that is still not presented to us. What we need to know is how controlReg0 and statusReg1 is defined in topmodule. If they are defined as ports then you will not be able to manipulate them in your top module and I would expect that the registers exist in the sub-module only. It would looks something like this:

entity topmodule is    port (     controlReg0 : in std_logic_vector(31 downto 0);     statusReg1 : out std_logic_vector(31 downto 0));end entity topmodule;architecture behave of topmodule isCOMPONENT submodPORT(controlReg0 : IN std_logic_vector(31 downto 0);statusReg1 : OUT std_logic_vector(31 downto 0));END COMPONENT;begintest : submodport map (controlReg0 => controlReg0,statusReg1 => statusReg1)end behave;

If you need to manipulate those registers in the topmodule then you would have to do something like this:

entity topmodule is	port (	 controlReg0 : in std_logic_vector(31 downto 0);	 statusReg1 : out std_logic_vector(31 downto 0)  );end entity topmodule;architecture behave of topmodule isCOMPONENT submodPORT(controlReg0 : IN std_logic_vector(31 downto 0);statusReg1 : OUT std_logic_vector(31 downto 0));END COMPONENT;signal  controlReg0_local:    std_logic_vector(31 downto 0);signal  statusReg1_local:    std_logic_vector(31 downto 0);begintest : submodport map (controlReg0 => controlReg0_local,statusReg1 => statusReg1_local)controlReg0 <= controlReg0_local;statusReg1 <= statusReg1_local;end behave;

You can then manipulate and make changes to controlReg1_local and statusReg1_local in your topmodule. In this case there will be two registers...

 

Hope this helps,

Jack.

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Jack,

Thanks for the info.

 

Actually the controlReg0 and statusReg1 were not ports in the top level module, the only top level module port was the bus, which is why I didn't include in the top level port command I posted in the first message.

 

So controlReg0 and statusReg1 were just signals defined in the top level module. They were used in the port command for the submodule though.

 

That was what was so confusing about the code. It was much different than what I have seen how a lot of the wishbone vhdl code handles buses.

 

The way I read it was that the bus is the only thing coming into the top level module. Then the bus and the registers are in the port to the sub module. It was like they designed the submodule to handle processing the registers.

 

I think I will just build up a minimal test with a microblaze and try it out to see how it works and why they built it that way.

 

Thanks to you and Alvie for the info,

Chris

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