Hugo Sereno Ferreira Posted March 1, 2014 Report Share Posted March 1, 2014 I am attempting to convert the Logic Analyser to work on a Papilio Pro. Attached are my best efforts so far; ISE fails to build at some point with a cryptic error message: Optimizing unit <BRAM6k8bit> ...WARNING:Xst:2677 - Node <Inst_core/Inst_sampler/ready50> of sequential type is unconnected in block <Logic_Sniffer>.INTERNAL_ERROR:Xst:cmain.c:3423:1.29 - Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. Thoughts?VHDL_Core.zip Link to comment Share on other sites More sharing options...
Hugo Sereno Ferreira Posted March 1, 2014 Author Report Share Posted March 1, 2014 Now that's strange... The error disappeared once I booted into Windows (was running ISE on a OSX with Wine). I'll let you know if I was successful in running the design. Link to comment Share on other sites More sharing options...
Hugo Sereno Ferreira Posted March 2, 2014 Author Report Share Posted March 2, 2014 Well... almost... it seems that communications are working, since the software makes sense of the protocol (capture times also match).But, no matter what I connect the ports into, they always return the same result (in attach). I also attach the latest project. VHDL_Core.zip Link to comment Share on other sites More sharing options...
Hugo Sereno Ferreira Posted March 2, 2014 Author Report Share Posted March 2, 2014 Well, now I feel a little stupid to find out that this project is already available as a sketch in the new ZPUino IDE :-) Link to comment Share on other sites More sharing options...
Jack Gassett Posted March 2, 2014 Report Share Posted March 2, 2014 I just got online and saw this thread, I was going to tell you that there is an 8-bit version ready to go in the ZAP IDE/Papilio Schematic Library. Glad you found it. I'll be working on a 32 channel version soon. Jack. Link to comment Share on other sites More sharing options...
Hugo Sereno Ferreira Posted March 2, 2014 Author Report Share Posted March 2, 2014 The idea of having ZAP to act as a central IDE to those schematics is *genial*. Well done, sir! I'm having some difficulties in opening the Bench Sump Logic Analyser in ISE though: ERROR: Failed to load symbols for C:\Papilio-Schematic-Library-1.6\examples\Benchy_Sump_LogicAnalyzer\Papilio_Pro.sch no netlist will be generatedERROR: Could not find symbol "Papilio_Wing_Pinout"ERROR: Could not find symbol "Wing_GPIO"ERROR: Could not find symbol "Wishbone_Empty_Slot"ERROR: Could not find symbol "COMM_zpuino_wb_UART"ERROR: Could not find symbol "ZPUino_Papilio_Pro_V1"ERROR: Could not find symbol "BENCHY_sa_SumpBlaze_LogicAnalyzer8"In the tutorial page you mention a base project, but it seems the information is already out-of-date in the 1.6 schematic library. Link to comment Share on other sites More sharing options...
Jack Gassett Posted March 2, 2014 Report Share Posted March 2, 2014 Yes, things are moving so quickly that the documentation is falling behind. I'll get it all updated soon though, right now I'm trying to lay down the groundwork for how everything works. For the problem you are having you need to add the location of the schematic symbol library in ISE. Go to this tutorial and scroll down a little bit until you get to the section that says, "To add the schematic symbol library we need to go to Tools/Symbol Library Manager." Follow that section and you should be good to go. If you have an older version of the Papilio Schematic Library installed then you might need to delete it from your system. ISE is not very good with dealing with libraries so I've had to experiment with different ways of doing things. Oh, I just realized that it is not obvious where the schematic symbol library is now. It should be located in zap/examples/00.Papilio_Schematic_Library/Libraries/Xilinx_Symbol_Library I better update that getting started guide asap. Let me know if there are any other problems. Jack. Link to comment Share on other sites More sharing options...
Hugo Sereno Ferreira Posted March 2, 2014 Author Report Share Posted March 2, 2014 Actually, I don't have that option in the menu :-\ I'm using ISE Webpack 14.6 (free version). Link to comment Share on other sites More sharing options...
mkarlsson Posted March 2, 2014 Report Share Posted March 2, 2014 Or you could try the attached bit file which uses the latest Open Bench Logic Sniffer code (Verilog Demon 3.07) ported to Papilio-Pro. Magnuslogic_sniffer.bit Link to comment Share on other sites More sharing options...
Jack Gassett Posted March 3, 2014 Report Share Posted March 3, 2014 Actually, I don't have that option in the menu :-\ I'm using ISE Webpack 14.6 (free version). Hugo, you have to open up the schematic window first before you see the option show up under the tools menu. Link to comment Share on other sites More sharing options...
jancumps Posted June 30, 2014 Report Share Posted June 30, 2014 Or you could try the attached bit file which uses the latest Open Bench Logic Sniffer code (Verilog Demon 3.07) ported to Papilio-Pro. MagnusWhat is the source for this bit file?This one: http://www.gadgetfactory.net/2011/03/openbench-logic-sniffer-3-07-demon-core-release/ ? Link to comment Share on other sites More sharing options...
mkarlsson Posted June 30, 2014 Report Share Posted June 30, 2014 It's based on Verilog Demon 3.07 but with modifications to use serial i/o instead of SPI. See this thread for more info and source code:http://forum.gadgetfactory.net/index.php?/topic/1720-demon-307-ported-to-p1-250-500/#entry11322 The only change I made for Papilio Pro was to remove the advanced triggers since that code is written using primitives only found in Spartan3 and if compiled for Spartan6 LX9 it wont fit. Magnus Link to comment Share on other sites More sharing options...
jancumps Posted June 30, 2014 Report Share Posted June 30, 2014 It's based on Verilog Demon 3.07 but with modifications to use serial i/o instead of SPI. See this thread for more info and source code:http://forum.gadgetfactory.net/index.php?/topic/1720-demon-307-ported-to-p1-250-500/#entry11322 The only change I made for Papilio Pro was to remove the advanced triggers since that code is written using primitives only found in Spartan3 and if compiled for Spartan6 LX9 it wont fit. MagnusThank you. Checking the other thread... Link to comment Share on other sites More sharing options...
jancumps Posted August 16, 2014 Report Share Posted August 16, 2014 Magnus, Do you have a version of the Pro port project source available?As a follow up on this thread ,I'd like to check how to change the pulldown settings for the Pro. I haven't been successful in replicating your port to Pro starting from the source code you refered to here . Link to comment Share on other sites More sharing options...
offroad Posted August 16, 2014 Report Share Posted August 16, 2014 I'm interested, too :-) The P. Pro version works fine for me but I'd rather remove the pull-ups for electrical debugging, if it comes to that.I might also enable the protection diodes, as outlined here on page 20: http://www.xess.com/static/media/manuals/XuLA2-manual.pdf Link to comment Share on other sites More sharing options...
mkarlsson Posted August 16, 2014 Report Share Posted August 16, 2014 Sure. See attached zip file for the complete XISE project (ISE 14.4). The .ucf file do have pulldowns enabled on the inputs Note that the advanced triggers (aka HP16500 triggers) are commented out in this version in order for it to fit into the Spartan6 LX9. The code for this is written using a CLB primitive only found in Spartan3 (SRLC16E) and when synthesized for Spartan6 this primitive is replaced with common logic blocks which takes up way more space. Magnus Papilio_Pro_OLS.zip Link to comment Share on other sites More sharing options...
offroad Posted August 16, 2014 Report Share Posted August 16, 2014 Thanks, builds fine on 14.7.No more trial-and-error to locate input xyz... almost too easy... Link to comment Share on other sites More sharing options...
jancumps Posted August 16, 2014 Report Share Posted August 16, 2014 Great, I'm going to do a diff with the code for the One to learn where the porting attempt is. I had these errors when switching your original code to X6, but was not sure how to handle that:ERROR:MapLib:30 - LOC constraint P4 on indata<23> is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P3 on indata<22> is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P91 on indata<16> is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P89 on bf_clock is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P86 on indata<15> is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P53 on indata<6> is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P18 on indata<0> is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P63 on extTriggerOut is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P90 on tx is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P25 on armLEDnn is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.Diffing may give me a lead on how you do that. Eager to learn. Link to comment Share on other sites More sharing options...
mkarlsson Posted August 16, 2014 Report Share Posted August 16, 2014 The PapilioPro.ucf file (user constraint file) specifies to which pins the signals are mapped to. The Spartan6 on Papilio Pro uses different pins that the Spartan3E on Papilio One. Magnus Link to comment Share on other sites More sharing options...
jancumps Posted August 16, 2014 Report Share Posted August 16, 2014 I've rebuild and tested an i2c circuit with and without pulldowns: (tested by altering A0 and A1 as follows):# indata[0-15] mapped to Wing A[0-15]NET "indata[0]" IOSTANDARD = LVCMOS33;....NET "indata[1]" IOSTANDARD = LVCMOS33;.....With pulldowns configured for A0 and A1: i2c signals approx 1 volt down NewFile1.bmp without pulldowns for A0 and A1: virtualy no impact on signal NewFile0.bmp Link to comment Share on other sites More sharing options...
jancumps Posted August 16, 2014 Report Share Posted August 16, 2014 Bit file for the Papillio Pro with pulldowns disabled,based on Magnus' projectLogic_Sniffer.bit And the constraints filePapilioPro.ucf.tar.gz Link to comment Share on other sites More sharing options...
jancumps Posted August 16, 2014 Report Share Posted August 16, 2014 ...I might also enable the protection diodes, as outlined here on page 20: http://www.xess.com/static/media/manuals/XuLA2-manual.pdf I'm using (my own implementation of) an IOBuffer wing to get the Papilio 5v tolerant. Link to comment Share on other sites More sharing options...
mkarlsson Posted August 16, 2014 Report Share Posted August 16, 2014 Another option is to get the 32-bit OLS buffer wing for Pipistrello, With some tweaks to the ucf file it will work for Papilio as well.http://saanlima.com/store/index.php?route=product/product&product_id=55 Magnus Link to comment Share on other sites More sharing options...
jancumps Posted August 16, 2014 Report Share Posted August 16, 2014 I have seen this board while troubleshooting my build of the IOBuffer - I have been thinking about going for the NPX/Philips IC for my implementation, but landed with the TI one (and that works fine). Inspired by the Pipistrello wing, I might change the constraint file of the Pro project you loaded here to use the 'C wing' connector for 16-31 too in stead of the 'B wing'.In my PCB design for the buffer I did not place the wing headers exactly on the board edge, so I can't plug one into 'A' and one into 'B'. Link to comment Share on other sites More sharing options...
guermazi_zied Posted January 10, 2015 Report Share Posted January 10, 2015 HiPapilio Pro has 8MB additional SDRAM. using it for storing samples is interesting since it increases the recording size. did someone succeeded in using it for storing the samples instead of the BRAM? /Zied Link to comment Share on other sites More sharing options...
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