coryjfowler

LogicStart MegaWing 7 Segment Display Has No Current Limiting...

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I'm very new to VHDL "programming" and was going though Mike Feild's eBook at my own pace.  Using one of the displays at 100% duty cycle has caused it to be noticably dimmer than the other three once I got them all working together...  I wondered why this would be so I dug up the schematic and to my dismay, there is nothing to limit the current going through the segments and, even worse, the transistors have no current limiting on the base junction.  Its also worth noting that the display gets warm during operation.  Had I known this before I began tinkering with the board, I probably would have been a lot more careful with it.  Considering this is something that beginners will be using, this is a very bad design...  I also seem to have burnt out one of the decimal points as only three of the four light up now.

 

I can see that about ~0.2V would be dropped across the anode transistors' CE junction at saturation and the segments themselves will drop 2.0 to 2.4V but, still, there is no current limiting...  LEDs are voltage devices, not current devices; as long as the LED has enough voltage to initiate conduction it will allow the maximum current that the conducting path permits which only seems to be limited by the FPGA in this case. That can equally be as bad for the FPGA, but what is worse is the anode transistors not having a current limiting resistance means the FPGA has ~2.1V across the anode pin and ground when it is active and, again, with the FPGA being the sole current limiting factor...

 

While changing the duty cycle of the display would be a soultion, how many beginners will be thinking of this when all they want to see is the thing show some numbers?

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I'm very sorry for the trouble you are having with the LogicStart, if you send us an email to support@gadgetfactory.net with your shipping address we will send you out a replacement board right away. Please reference this forum thread in the email.

 

Sincerely,

Jack.

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I've also lost a segment off my 7-seg display - mine was also running extremely hot - should have looked into it more deeply... bugger :/

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Jack: perhaps we should limit the PWM duty on our ZPUino controller to 80% or so, although people driving the segments with HDL will surely run into the same issue....

 

Alvie

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I think there are two things that are in the works to address this problem. 

 

1) There is a new design that is ready with current limiting resistors. But, it takes time to get a new version released and it has to be carefully staged to account for the existing stock.

2) The DesignLab software will allow us to publish reference designs that will safely drive these displays. Hopefully people will start there experimenting with these new HDL designs.

 

Jack.

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While current limiting resistors calculated for continuous drive will limit the brightness to somewhat below what could otherwise be supported with a multiplexed display, it's an acceptable compromise. I also noticed the lack of current limiting and while I've been careful in order to prevent damage to the display on mine, it certainly is poor design practice. LEDs should *always* have current limiting, as should the drive to the transistors. As it is, it's relying on the internal resistance of the FPGA output pins to prevent the transistors from burning out.

 

I've resorted to adding code to ensure that all the anodes are switched off to any design not using the displays. Otherwise unused signals are sometimes routed to those pins causing random segments to light brightly.

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In my defense, I looked at several Xilinx reference designs when I made the LogicStart. Several of them do not have current limiting resistors on the 7 segment display...

 

Jack.

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I bet those reference designs were not aimed at letting beginners fry control the LEDs :) Nevermind, live and learn.

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I'm betting they were meant to show off the drive limiting capabilities of the FPGA pins. It's a reasonable solution for a production design, but not very robust for a learning system that will be abused.

 

Is there a place on the board where some segment protection resistors could be added without hacking things up too much? Cut the trace, solder a chip resistor across the gap?

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Jack

 

Any chance you could link to the actual 7 seg display part used on the LogicStart boards? Ideally with an RS/E14/Digikey part number?

 

After some digging I think it's just one of these

 

Just want to make sure if/when I burn mine out ;)

 

Also, on a semi related note, from what I can tell the central colon on the disply isn't actually connected on the LogicStart board, is that correct?

 

Thanks

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Wendo, that is indeed the correct link for the 7 segment display. I never found the correct one at Digikey, so I order from Sparkfun when I need them and my manufacturers buy in bulk from a Chinese supplier.

 

Jack

 

Also, on a semi related note, from what I can tell the central colon on the disply isn't actually connected on the LogicStart board, is that correct?

 

 

The central colon is not connected, we ran out of pins unfortunately.

 

Jack.

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Did anyone eventually work out what a good safe drive and pulse width/duty cycle for this were.

 

I'm running mine as LSTTL (and not sure I can change that without ISE bitching about conflicts) and with a 10% duty cycle at 31.25Khz but it still seems a bit bright ?

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Did anyone eventually work out what a good safe drive and pulse width/duty cycle for this were.

 

I'm running mine as LSTTL (and not sure I can change that without ISE bitching about conflicts) and with a 10% duty cycle at 31.25Khz but it still seems a bit bright ?

 

A generic datasheet (http://www.wayjun.com/Datasheet/Led/Segment%20Digit%20LED%20Display.pdf, page 32) indicates that 50mA @ 10% duty at 10 Hz  is within spec. 50mA is about the short circuit current of a I/O pin. (changing the "drive" attribute of the pin can change this a little, but DRIVE=2 doesn't limit the current to 2mA!)

 

I've been driving each digit at 1/16 duty cycle, at about 61 Hz.

process(clk)   begin      if rising_edge(clk) then         case counter(18 downto 15) is            when "0000" => seg_anodes   <= "1110"; seg_segments <= seg0; seg_dp <= not decimals(0);            when "0001" => seg_anodes   <= "1101"; seg_segments <= seg1; seg_dp <= not decimals(1);             when "0010" => seg_anodes   <= "1011"; seg_segments <= seg2; seg_dp <= not decimals(2);            when "0011" => seg_anodes   <= "0111"; seg_segments <= seg3; seg_dp <= not decimals(3);            when others => seg_anodes   <= "1111";         end case;          counter <= counter+1;       end if;   end process;end Behavioral;

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Thanks I'm currently driving them at about 32Khz 10% duty cycle might try a lower cycle then.

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