alex

Yet another VHDL CPU core

7 posts in this topic

Good old Hack-a-Day made me spend more money on this Indiegogo Campaign for a super cheap GPS board.

20131205031054-pin_func.jpg?1386241854

 

In any case researching the components on that board it seems the Venus 822 GPS chip they they are using is an ASIC that incorporates a Leon3 processor. Tracking that down to the supplier web site I see the VHDL core is downloadable:

 

The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs. The full source code is available under the GNU GPL license, allowing free and unlimited use for research and education. LEON3 is also available under a low-cost commercial license, allowing it to be used in any commercial application to a fraction of the cost of comparable IP cores. The LEON3 processor has the following features:

  • SPARC V8 instruction set with V8e extensions
  • Advanced 7-stage pipeline
  • Hardware multiply, divide and MAC units
  • High-performance, fully pipelined IEEE-754 FPU
  • Separate instruction and data cache (Harvard architecture) with snooping
  • Configurable caches: 1 - 4 ways, 1 - 256 kbytes/way. Random, LRR or LRU replacement
  • Local instruction and data scratch pad RAM, 1 - 512 Kbytes
  • SPARC Reference MMU (SRMMU) with configurable TLB
  • AMBA-2.0 AHB bus interface
  • Advanced on-chip debug support with instruction and data trace buffer
  • Symmetric Multi-processor support (SMP)
  • Power-down mode and clock gating
  • Robust and fully synchronous single-edge clock design
  • Up to 125 MHz in FPGA and 400 MHz on 0.13 um ASIC technologies
  • Fault-tolerant and SEU-proof version available for space applications
  • Extensively configurable
  • Large range of software tools: compilers, kernels, simulators and debug monitors
  • High Performance: 1.4 DMIPS/MHz, 1.8 CoreMark/MHz (gcc -4.1.2)

 

 

 

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I know well LEON3 and LEON2, I worked with them for some projects with the European Space Agency. I have most of the code for the GRLIB also, but of course cannot share it with you guys. The cores are however open-source, but you won't want them implemented on a cheap FPGA. The best I got with LEON2 with FPU (Meiko) was ~80MHz on a ML507 board (Virtex-5). For reference, that board costs >$1200.

 

SPARC is an interesting but complex platform. I will not advise any one to work with it in low-level. The register windows and WOF/WUF are a pain.

 

Most of LEON cores (Gaisler) were sponsored by the European Space Agency. ESA uses mostly ERC32 for space, but they are not developed anymore, and LEON3FT is to be used for upcoming missons, once it's approved internally. ESA has also a multi-core project, called NGMP, which is AFAIK based on LEON3.

 

Alvie

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Another note: What I really liked in Leon2/3 was the (proprietary) GRMON [1]. This is a full-featured debug interface, which works with several transport mechanisms, like ethernet and RS232. I could have not close the xLuna project without it (and without GRSIM [2]).

 

The best I ever seen, but to be honest was the only commercial one I ever used. I assume ARM debuggers (>$5K for sw and hw) would work even better.

 

Alvie

 

[1] http://www.gaisler.com/index.php/products/debug-tools/grmon, http://www.gaisler.com/index.php/products/debug-tools/grmon2

[2] http://www.gaisler.com/index.php/products/simulators/grsim

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Update: I still have the Leon2 figures here, with FPU and ethernet:

 

Target Device  : xc5vsx50t

  Number of Slice LUTs:                     13,284 out of  32,640   40%

  Number of occupied Slices:                 6,049 out of   8,160   74%

 

Big, big :)

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hello,

Actually i am working in SPARC V8 .Can u guide me i have the grlib-gpl-1.5.0-b4164 folder .With what u hv worked

I want to synthesize the design in XILINX but i am not getting the procedure can u plz guide me

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On 1/18/2014 at 8:11 PM, alvieboy said:

...

The best I ever seen, but to be honest was the only commercial one I ever used. I assume ARM debuggers (>$5K for sw and hw) would work even better.

...

Just wondering: Do you know the Microblaze debugger that comes with Web-edition Vivado?

I've used the basic features (breakpoints, step, edit variables etc) on an Artix. It was surprisingly simple and usable without having read any manual.

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No, I never used Microblaze at all. I find the architecture (most notably the function preambles/postambles for C ABI) a bit awkward.

And it's commercial :)

Alvie

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