mkarlsson

Open Bench Logic Sniffer with 64MB capture buffer

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A new version of the Open Bench Logic Sniffer code is now available for Pipistrello. This version has the capture buffer increased to 64 MB by using the onboard LPDRAM instead of using internal BRAM. The capture rate is still the same, i.e. it still support 200 MHz 8 and 16-bit capture as well as 100 MHz 32-bit capture. The serial communication speed is set to 921600 baud.

 

The original SUMP protocol unfortunately has a capture size limitation (in both hardware and software) to a maximum of 256k samples (512k samples in mux mode). This version of the verilog code has an alternative set of capture size registers that will allow up to 256M samples. However, the SUMP client on the PC must be modified to take advantage of the new registers so I have modified JaWi's OLS client to allow longer captures. BTW, the bit file will also work with the current release of the SUMP client but with the capture size limitation mentioned above.

 

Here is a link to a zip file that has the bit file, the full Xilinx ISE project and the modified version of JaWi's OLS client:

http://www.saanlima.com/download/pipistrello-v2.0/Pipistrello_OLS_64M.zip

 

Enjoy!

 

BTW, if anyone is interested in using the built-in DRAM memory controller in Spartan-6 parts this code might be a good starting point. It's setup to use one 64-bit read/wire port but this can be changed by using different parameters when instantiating the memory controller block.

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A quick question, any reason why the serial speed can't be pushed much higher? I believe with VCOM ports you could go to 2M baud at least.

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I did 921600 because that's how high the current release of JaWi's OLS client can be set.

 

I think the real solution is to use FIFO mode instead of serial.  Pipistello_v2 supports async FIFO mode which will go up to about 9 MB/sec so a full 64MB dump will take about 7 sec. which I think is reasonable.

(I did port the code to Pipstrello_v1 using sync FIFO mode and got over 29 MB/sec transfer speed.)

 

In order to use FIFO mode the SUMP client would need to have support for this.  I have been in contact with Jan William (the author of the JaWi OLS client) and he is interested in adding FIFO mode as an option, enough to buy a Pipistrello board :)

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I saw the excellent idea that Jack got to use the OLS-client's network interface to talk to a small socket server that then uses JTAG to talk to the FPGA, so I decided to use the same idea but instead talk to Pipistrello via the FTDI async fifo interface which should be much faster than using serial mode (see above).  This is definitely work in progress but it's quite useful at this point.

 

Here is how to set this up (currenlty windows only):

 

1) Download and unzip the attached zip file.  It contains Pipistrello sniffer bit files as well as binary and source files for the programs used (with batch files to kick them off).

2) You need to change the Pipistrello FTDI eeprom setting to switch from serial to async-fifo mode using a program called setmode.  The batch file set_fifo.bat will do that for you.
3) Power-cycle the board to reload the eeprom setting
4) Load the fifo version of the logic-sniffer bit file to the board (to flash or to ram) using flash_bitfile.bat or load_bitfile.bat
5) Start the server using start_server.bat
6) Start the OLS client and select Network connection type to localhost at port 5000
7) Capture data

 

Use set_uart.bat to switch back the FTDI eeprom setting to serial mode.

The server is quite verbose at this point (similar to Jack's screenshot).

 

One limitation with this version of the code is that it's using blocking socket calls so it's not able to poll for reset commands from the OLS client while waiting for a trigger to happen.

 

Also note that the official version of the OLS client has a limitation of maximum 256k samples (this is actually a limitation in the SUMP protocol) so you need the modified version of JaWi's OLS client that has extended the SUMP protocol with 32-bit size registers.  Here is a link to that version (the file is too bit to attach):

http://www.saanlima.com/download/pipistrello-v2.0/ols-0.9.8-SNAPSHOT-full.zip

 

To capture and download 1 M samples of 32-bit data (i.e. 4 MB) takes less than a second so it's way faster than serial mode.  See attached screen shot.

 

Enjoy!

 

Magnus

Pipistrello_OLS_fifo.zip

post-36465-0-27411500-1390855580_thumb.p

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I saw the excellent idea that Jack got to use the OLS-client's network interface to talk to a small socket server that then uses JTAG to talk to the FPGA, so I decided to use the same idea but instead talk to Pipistrello via the FTDI async fifo interface which should be much faster than using serial mode (see above).  This is definitely work in progress but it's quite useful at this point.

 

Here is how to set this up (currenlty windows only):

 

1) Download and unzip the attached zip file.  It contains Pipistrello sniffer bit files as well as binary and source files for the programs used (with batch files to kick them off).

2) You need to change the Pipistrello FTDI eeprom setting to switch from serial to async-fifo mode using a program called setmode.  The batch file set_fifo.bat will do that for you.

3) Power-cycle the board to reload the eeprom setting

4) Load the fifo version of the logic-sniffer bit file to the board (to flash or to ram) using flash_bitfile.bat or load_bitfile.bat

5) Start the server using start_server.bat

6) Start the OLS client and select Network connection type to localhost at port 5000

7) Capture data

 

Use set_uart.bat to switch back the FTDI eeprom setting to serial mode.

The server is quite verbose at this point (similar to Jack's screenshot).

 

One limitation with this version of the code is that it's using blocking socket calls so it's not able to poll for reset commands from the OLS client while waiting for a trigger to happen.

 

Also note that the official version of the OLS client has a limitation of maximum 256k samples (this is actually a limitation in the SUMP protocol) so you need the modified version of JaWi's OLS client that has extended the SUMP protocol with 32-bit size registers.  Here is a link to that version (the file is too bit to attach):

http://www.saanlima.com/download/pipistrello-v2.0/ols-0.9.8-SNAPSHOT-full.zip

 

To capture and download 1 M samples of 32-bit data (i.e. 4 MB) takes less than a second so it's way faster than serial mode.  See attached screen shot.

 

Enjoy!

 

Magnus

 

 

Magnus, I'm curious how you have this all setup... Can you show how you have the bscan primitive connected? When you change from MPSSE mode to async FIFO mode it stays in USER1 in order to pass the signals through? Any information/tricks about the bscan primitive is like gold. :)

 

 

Thanks,

Jack.

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Ohhhh! I understand, you are not using JTAG, you are using the socket server to implement the fast async FIFO interface... ok, ok.... I was thinking you were using Channel A and converting the JTAG pins to an async FIFO.

 

If the OLS client used the FTDI libraries directly and implemented the async FIFO mode then there would be no need for this server, but until they do this is a gateway to enable faster speeds.

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You are welcome to use any of the code.  It's based on something I pulled down from the net :)

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I just wanted to let you know I have been working on adding support for Pipistrello OLS in sigrok and pulseview.
Sigrok and the gui frontend PulseView is a very actively developed open-source interface for all kinds of logic analyzers, scopes, multimeters etc.
See:http://www.sigrok.org/

sigrok-cli is the command-line version and pulseview is a Qt-based GUI frontend. Pulseview still has a way to go to be complete (it still misses trigger setup) but the drawing part is amazingly good and very fast (it handles 16 Meg 32-bit samples flawless). It's developed on linux but you can cross-compile for windows.

If you want to give it a try on windows here is how to get it installed. The tricky part is that you need to change the USB driver for the board to libusb-win32. I admit this is somewhat scary but it worked for me using the filter driver and I can still access the board via the FTD2xx driver for other use (like fpgaprog) etc., but you do this on your own risk. For more info in this see: http://www.sigrok.org/wiki/Windows

Steps (this assumes you have the fifo-version of the OLS code loaded on Pipistrello and it's set to use FTDI fifo mode):

1) Download and run the pulseview installer from here: http://www.saanlima.com/download/pulseview-0.2.0-installer.exe
2) Connect the Pipistrello board to the computer
3) Go to c:\Program Files (x86)\sigrok\PulseView and run zadig.exe
4) In the Zadig GUI select "Options -> List All Devices
5) Select "Pipistrello LX45 (Interface 1) " as the device. You should see USB ID as 0403:6010:01
6) Change the new driver from WinUSB to "libusb-win32"
7) Next to the "Replace Driver" button there is a pulldown menu marked by an arrow. Pull it down and select "Install filter driver"
8) Click on "Replace Driver". There is a warning popping up, select OK.
9) Run Pulseview from the start button. It should come up with demo device selected. Change device to Pipistrello OLS.
10) Next to the device pulldown button there is now a new button marked with a screwdriver and wrench. Click on it and select "External" as the pattern.
11) Change the sample rate to 100 MHz and click on the Run button. After about a second you should see the traces show up with the test pattern on ch 16 - 31.

For Linux you have to compile from sources. See http://sigrok.org/wiki/Linux for info on building it on Linux.
My source code for libsigrok with Pipistrello OLS support is available at github:
https://github.com/magnuskarlsson/libsigrok

My verilog source for the Pipistrello OLS is also available at github:
https://github.com/magnuskarlsson/Pipistrello_ols_verilog

Bit files (and a complete Xilinx ISE project) can be found here:
http://www.saanlima.com/download/pipistrello-v2.0/Pipistrello_OLS_64M_fifo_05282014.zip
See the README file in the zip archive for more info.

 

EDIT:  The links above have been updated to the latest code with edge trigger support.

Magnus

post-36465-0-83100100-1398889443_thumb.p

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I managed to perform a full sigrok build on Ubuntu 12.04 using the instructions from http://sigrok.org/wiki/Linux, and execute PulseView.

That didn't give me the OLS as an option in the device list.

 

So I tried building sigrok/pulseview according to Magnus' explanation above.

 

When I tried to use Magnus' Pipistrello github for libsigrok in stead of the default one, by replacing

git clone git://sigrok.org/libsigrok

with

git clone git://github.com/magnuskarlsson/libsigrok.git

compilation of the libsigrok went fine, but subsequent compilation of libsigrokdecode failed:

libsigrokdecode configuration summary:  - Package version (major.minor.micro):    0.3.0  - Library version (current:revision:age): 2:0:0  - Prefix: /usr/local  - Building on: i686-pc-linux-gnu  - Building for: i686-pc-linux-gnuDetected libraries:  - (REQUIRED) python >= 3.2: yes (3.2)  - (REQUIRED) glib-2.0 >= 2.24.0: yes (2.32.4)  - (OPTIONAL) check >= 0.9.4: yes (0.9.8)  - (OPTIONAL) libsigrok >= 0.3.0: yes (0.3.0)Enabled features:  - (OPTIONAL) Library unit test framework support: yes  - (OPTIONAL) Protocol decoder test framework support: yesjan@ramsel-starbase-hq:~/sigrok/libsigrokdecode$ makemake  all-am  CC     libsigrokdecode_la-srd.lo  CC     libsigrokdecode_la-session.lo  CC     libsigrokdecode_la-decoder.lo  CC     libsigrokdecode_la-instance.lo  CC     libsigrokdecode_la-log.lo  CC     libsigrokdecode_la-util.lo  CC     libsigrokdecode_la-exception.lo  CC     libsigrokdecode_la-module_sigrokdecode.lo  CC     libsigrokdecode_la-type_decoder.lo  CC     libsigrokdecode_la-type_logic.lo  CC     libsigrokdecode_la-error.lo  CC     libsigrokdecode_la-version.lo  CCLD   libsigrokdecode.la  CC     tests/tests_runtc-runtc.otests/runtc.c: In function ‘run_testcase’:tests/runtc.c:351:2: error: too many arguments to function ‘sr_session_load’  if (sr_session_load(infile, &sr_sess) != SR_OK)  ^In file included from /usr/local/include/libsigrok/libsigrok.h:968:0,                 from tests/runtc.c:22:/usr/local/include/libsigrok/proto.h:87:12: note: declared here SR_API int sr_session_load(const char *filename);            ^tests/runtc.c:356:2: warning: passing argument 1 of ‘sr_session_datafeed_callback_add’ from incompatible pointer type [enabled by default]  sr_session_datafeed_callback_add(sr_sess, sr_cb, sess);  ^In file included from /usr/local/include/libsigrok/libsigrok.h:968:0,                 from tests/runtc.c:22:

my GCC version: 4.8.1

commands attached as build.sh, fails on line 37 (make after cloning Magnus' github and running autogen and config successfull.

 

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This is due to version mismatch between libsigrok and libsigrokdecode.

 

There is a lot of development going on with sigrok.  When you do "git clone git://sigrok.org/libsigrokdecode" etc. you will get the latest developent version of the code (aka master), not the official release version.

 

The libsigrok code in my github repository is based on the latest official release of the sigrok components and to use that you will need the official release version of all the sigrok components, for libsigrokdecode that's libsigrokdecode-0.3.x instead of master.

 

See the change history on this page: http://sigrok.org/gitweb/?p=libsigrokdecode.git;a=summary

A few days ago there was a change in the session API...

 

For the source code of the latest sigrok release (in tar.gz format) see this link: http://www.sigrok.org/blog/new-major-release-various-sigrok-components

 

Hope this helps.

 

Magnus

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Do you guys think sigrok and pulseview are better then the OLS client? I haven't looked at them in a while so was just curious what the latest versions look like.

 

Jack.

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I'm happy with the OLS client. I got interested in sigrok when I saw what dreamsourcelab.com made of it (http://www.dreamsourcelab.com/dslogic.html).

I tried buiding it from source. It worked, but I couldn't get the sniffer support working (see above). I'll check Magnus' comments and try to build with the latest sigrok release sources and the libraries from Magnus' github repository...

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I might use your server code, mine is pretty ugly...

Hi, Jack;

 

I wonder if you might share 1) source for your server, 2) perhaps configuration details / examples for the FT2232D, and 3) HDL for the fpga I/O to make this all work. I'm very curious about exactly how this communications path works. A forum link, or links, would be fine if you've already documented it.

 

Thanks in advance.

 

dandreat

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Looks like the Pipistrello is back in stock... I guess it will be the perfect logic analyzer to hunt bugs in my Papilio Pro designs. Not that they include any. I mean logic  :-)

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