james1095

Noob question about data buses

5 posts in this topic

If I want to use a softcore, for example the T65 which has separate data-in and data-out buses with a soft (or hard) peripheral with a single bidirectional data bus what is the recommended way of doing that? Can I assign data in and data out to the same signal, or do I need to conditionally assign based on the state of a read/write enable signal?

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James,

 

Inside the FPGA you have to go with separate input and output buses. High-Z, which is required for bi-directional buses, only works on external FPGA pins. You cannot use high-z inside the FPGA, so you will always see input and output separated. It actually makes things easier anyway, you don't have to write logic to control whether the lines are being used as input or output. There are plenty of resources available inside the fpga so there is no real reason to try to use bidirectional lines. Its only when we get to the external world that we start having pin constraints.

 

Jack.

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I did recall that tristate was not supported internally with modern FPGAs but I wasn't sure whether the software was smart enough to work around it or not. I'm still not entirely sure how to deal with code blocks that are already implemented with bidirectional buses though. Take the 6532 RIOT that is incorporated into the A2601 project for example. Do I have to write logic to control whether the data bus on that is connected to data in or data out of the T65 CPU? I haven't quite wrapped my brain around situations like this.

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Your first post is right on the money, read the bi-dir bus when it is configured as an output and write it when it is configured as an input, based on the bus' read/write status line if it has one.

 

As Jack said, most FPGA cores are written with separate ins and outs for a bi-dir bus, in your specific instance, it might make sense to follow the bus to the core of the RIOT and separate it into read and write data paths if no read/write signal exists. Also TIA has bi-dir bus too.

 

Just wondering, since the A2601 project already has a CPU core that works, why are you messing about with T65?

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Ok I think that clears things up, thanks! I was looking over the code for the 6532 and it looks like it ought to be fairly easy to modify it to separate the data bus so either way may work.

 

As for the choice of CPU cores, it seemed like a wash. I could use the 6502 core from the A2601 project which has a bidirectional data bus but then I'd have the same issue incorporating other blocks that have a split data bus. I'm also not as familiar with that core and wasn't sure how well it would do in a different application while the T65 core seems to be fairly widely used and well tested. I suspect either one would work just fine though. This is a learning exercise as much as anything. I'm starting to get the hang of things but I still have a ways to go before I can attempt to implement something more interesting from scratch.

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