Jack Gassett

Update to Papilio One Hardware Page

3 posts in this topic

Thank you for the heads up, I updated the page with the new URL. That page is a wiki page, so you can also feel free to make any updates or corrections by scrolling to the bottom of the page and selecting "edit page".

 

For the Tx and Rx pins, it depends on what perspective you are looking at the pins from, it gets confusing when you use the rx and tx naming because it will be reversed depending on whether you are talking about rx/tx from the fpga or rx/tx from the FT2232 chip. In the wiki page I refer to them as MOSI and MISO which I think is much clearer, Master Out Slave In and Master In Slave Out.

 

It shows that P88 is MISO so for the FPGA (the master) it is rx and the FT2232 (the slave) it is tx. P90 is MOSI so for the FPGA it is tx and the FT2232 it is rx.

 

Before I started thinking in those terms it was always a challenge to figure out the right configuration. You can't assume what the VHDL code you are using meant by rx/tx and I would always have to study the code to figure out what was right...

 

Jack.

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