Wishbone docs


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Is there any documentation on the specific version of Wishbone that ZPUino implements ?  All that the ZPUino docs state is that "ZPUino is Wishbone compliant", but the signals is uses don't seem to quite match any of the revisions of the spec that I'm able to find (e.g. no tag data).  Is there a simple description of the protocols that ZPUino modules should follow ?

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Going from memory, not all wishbone signals are mandatory. Also from memory the wishbone standard specifies that there should be documentation with every wishbone compliant design that shows what the mapping is between the signals in the actual design and the standard wishbone signal groups

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Hi bug,

 

ZPUino uses mostly "standard" b3 version, and supports both registered and unregistered cycles. But other more recent versions (like the ones which use external memory) use pipelined (B4) interfaces. The easiest way to tell one from the other is the presence of the "stall" control signal. This is only used for memory connections, the IO path is not pipelined (uses classical wishbone cycles).

 

alex: indeed, we should document more properly all the interfaces. Note that despite we using wishbone interfaces, we are not wishbone compatible yet because it's lacking documentation. Some devices can also exhibit non-compatible wishbone spec, because we simplified a few things: some devices do not respond to de-assert of "cyc" in order to simplify FSM implementation. But the master (ZPUino itself) does not perform de-assertion while the device is busy, so you're OK to go.

 

I hope this helps.

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