Jack Gassett Posted December 26, 2013 Author Report Share Posted December 26, 2013 I get the same error, I tried to look at all the obvious things like case sensitivity, but it seems like there is a bug in sch2hdl under linux... I'm going to have to figure out how to submit a bug report with Xilinx for this. In the meantime I discovered that if you export all of the symbols into the project directory you can proceed. To export the symbols do this: Tools/Symbol Library ManagerNextIn Add Symbols window, select all of the symbols and choose export to directory. Choose the project directory you want to synthesize.Finish the wizard and it will export all the symbols to your directory and you can proceed with synthesis. This is obviously not going to be a viable way for us to proceed, we need to get them to fix this bug under Linux... Jack. Link to comment Share on other sites More sharing options...
Peter Aus Wyk Posted December 26, 2013 Report Share Posted December 26, 2013 Hi Jack and thank you very much.... I did as you proposed and found the corresponding *.sym files in my project directory. Just for fun I copied them into the Xilinx Library Directory and deleted the sym-files after that in my project directory... eh voila it works I can live with that because it's only to be done once in the "template". For simplicity it may help others to put the *.sym files into the zip file? Many regards and thanks again, made my day Peter Link to comment Share on other sites More sharing options...
Jack Gassett Posted December 26, 2013 Author Report Share Posted December 26, 2013 Ah, that's good to know, I think I was actually doing earlier releases that way, but I think I removed that because it was causing problems under windows... Will have to take another look. Jack. Link to comment Share on other sites More sharing options...
Cloia Posted April 13, 2014 Report Share Posted April 13, 2014 Hi, +1 Argh ...I have got same error's . Debian 7x86_64 All schematic symbols need to be exported in root project folder ... Other problem see with C++ symbol in libstdc++ embed with Xilinx software Than very much too all. Regards, Link to comment Share on other sites More sharing options...
Peter Ivanov Posted January 18, 2015 Report Share Posted January 18, 2015 Hi, I'm using DesignLab-020, and want to synthesize zpu for Arcade MegaWing with pull-ups enabled for joystick inputs.I tried to copy schematic of Bricks example: ZPUino Soft Processor - Papilio One 500K - Vanilla -v2.0, HQVGA Adapter, VGA8 wing, clk_32to50dcm, VGA char map. Synthesize finishes, mapping returns with error (OVERMAPPED): Logic UtilizationUsedAvailableUtilizationNote(s)Number of Slice Flip Flops 2,035 9,312 21% Number of SLICEMs 9,609 2,328 412%OVERMAPPEDNumber of 4 input LUTs 27,356 9,312 293%OVERMAPPEDNumber of occupied Slices 14,071 4,656 302% OVERMAPPED Number of Slices containing only related logic 14,071 14,071 100% Number of Slices containing unrelated logic 0 14,071 0% Total Number of 4 input LUTs 27,573 9,312 296% OVERMAPPED Number used as logic 11,962 Number used as a route-thru 217 Number used as 16x1 RAMs 2,048 Number used for Dual Port RAMs 12,288 Number used for 32x1 RAMs 1,024 Number used as Shift registers 34 Number of bonded IOBs 55 66 83% Number of RAMB16s 20 20 100% Number of BUFGMUXs 5 24 20% Number of DCMs 3 4 75% Number of MULT18X18SIOs 3 20 15% Can anybody help? Regards,Peter EDIT: Sorry for wrongly displayed table. Link to comment Share on other sites More sharing options...
Jack Gassett Posted January 19, 2015 Author Report Share Posted January 19, 2015 **Sigh** There is always more work to be done... In this case the first problem you are running into is that HQVGA on the Papilio One 500K needs the Hyperion variant of ZPUino in order to work. Unfortunately I have not ported Hyperion to ZPUino 2.0 yet... It was working fine with ZPUino 1.0 in ZAP, but I decided to upgrade to ZPUino 2.0 for DesignLab and Hyperion was the one variant I didn't do. Hyperion uses less of the BRAM memory for code space so there is more available for the HQVGA adapter. With the vanilla version of zpuino on the P1 500K it uses all of the BRAM memory space for code so it is probably trying to use FPGA fabric as memory for the HQVGA and is going far, far over the resources it has available to do that... I'll see if I can get it up and running soon. Jack. Link to comment Share on other sites More sharing options...
Peter Ivanov Posted January 19, 2015 Report Share Posted January 19, 2015 I see. No problem, I've just changed the ucf of previous zpuino and the pull-ups work fine!I can understand that if you've got more boards and more extensions your work expontentially increases. I really appreciate your work and help. Regards,Peter Link to comment Share on other sites More sharing options...
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