Random data on JTAG interface


William MARTIN

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Hi,

 

I want to use a papilio Pro as dev board, before make my own.

In this futur board, i will not use a USB interface for the JTAG, but just a simple connector and a Bus pirate[1] in JTAG mode.

The bus pirate can be setup in a SPI mode too, it's allow communication between the FPGA and a computer.

 

If i share the same Bus pirate connector for the SPI interface and the JTAG interface, i will send random data on the FPGA JTAG when it's not in programming mode.

Does someone know what happen in this use-case ?

 

Thanks,

William MARTIN

 

[1] http://dangerousprototypes.com/docs/Bus_Pirate

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Well, I guess it could, with the Spartan chips the JTAG is always active... There is a method, the same one that is used by papilio-prog to program the SPI Flash, where you can put the JTAG TAP controller into USER1 and pass the JTAG pins through to other FPGA pins. You essentially pass the FT2232 MPSSE pins through and can use them for SPI/JTAG/Serial. It is a combination of setting up a SPARTAN_BSCAN primitive on the FPGA and having a control program on the PC put the FPGA into USER1 mode. The only example of doing this right now is the papilio-prog application, but theoretically it should work with any FT2232 based application such as FlashROM or OpenOCD.

 

Jack.

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This might be related to one situation I did encounter - FPGA reset after plugging the VGA connector with PPro and Arcade Megawing. I assumed some sort of interference with the reset (soft reset, not FPGA reset) line.

 

But I don't see any freeze with serial port, with ZPUino, even at 1Mbps.

 

Jack: perhaps 47K pullup is too high ? I just checked SP601 (Xilinx eval board for S6) and they use 4.7K.

 

Alvie

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To clarify, what I did was plug the FPGA into the USB port, then put the megawing on, then after running the command I noticed the space invader animation on the LCD froze, however replugging the SD card (Which I believe triggers a soft reset of the ZPU core in the FPGA not a reconfig of the FPGA) caused it to start working again, and not ammount of random data on that serial port would cause it to freeze again, so I suspect the only freeze I saw was me plugging the megawing into the running FPGA.

 

Besides, running the serial port like that would only put random data on one line of the JTAG port, and I believe the test reset line as well as other lines need to be interacted with to actually do anything.

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Yes, my instinct says that you could put random data on the JTAG pins all day and never see anything happen. There IS a chance that it will trigger a reset, or put the FPGA in USER1 or some state where it responds, but it would have to be a very specific random sequence for that to happen. I don't see any way you could damage the Papilio, or even realistically write anything to the SPI Flash.

 

Maybe you should go into more details about what it is you want to do?

 

Jack.

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Hmmm, perhaps so, I just checked the datasheet and the example shows 4.7k... Will have to put in a change request for the next batch of boards.

 

Jack.

If there are some components that are going to be changed over time, like "easy" ones as pullups etc, will you logg those, and have an writeup to what we can modify? as long as there are swapping of components, some of us should be able to do that on our own, instead of buying new units, that is, if it's issues that we can be/are affected by.

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If there are some components that are going to be changed over time, like "easy" ones as pullups etc, will you logg those, and have an writeup to what we can modify? as long as there are swapping of components, some of us should be able to do that on our own, instead of buying new units, that is, if it's issues that we can be/are affected by.

 

This change is so minor that it wouldn't be something that needs to be applied to previous Papilio Pro boards. A 4.7K resistor will just pull the line up a little stronger then a 47K resistor does. 47K is a very standard value for a pull-up resistor, if it was not working properly we would see the Papilio Pro resetting itself randomly, which we are not. Alvie saw something happen when he attached a MegaWing to a powered up board, which was not one of the design goals for the Papilio. Most companies just quietly make these types of changes without discussing them in public forums, but being open source we are more open about these types of things. Overall it's not something to be alarmed about. :)

 

Jack.

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I guess the best place to track changes like that is under the issues section on github. I will remember to log an issue there if I update the design so people can see the changes. I usually make a changelog file which I will make sure gets checked into the git repository too.

 

Thanks!

Jack.

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It was in the spirit of open source I was meaning, I'm not so sure if it is easy to diff eagle files

 

Actually it's SUPER easy now that Eagle 6.x has moved to .xml (text) files  :)

You can use "diff" in linux or the super awesome "Beyond Compare" in Windows which I use all the time to detect and review changes between entire folders (it even supports comparing against folders that are inside archives like zip or 7zip).

 

Disclaimer no I don't own shares in BC... haha

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We're getting off topic here, but that is strange. If you're expecting the file extensions to change, they won't, they're still called .sch and .brd but after loading a v5 file in eagle v6 and saving it, you will see the file size jump up (larger) and you could then open it with your favourite text editor and see actual text in it.

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Many thanks,

 

So the previous test confirm that they don't have issue to send random data to the JTAG port when the FPGA is not in programming mode.

 

And i can't test on a papilio one because the JTAG does not work the same way.

- Papilio One based on Spartan3e have a JTAG always on.

- Papilio Pro based on Spartan6 have a JTAG enable only when the push button reboot is pressed.

 

Right ?

 

William

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