Jack Gassett Posted March 6, 2012 Report Share Posted March 6, 2012 There have been so many inquiries about the Papilio Plus that we decided to do a short run of boards on our Pick and Place machine. Prototypes boards can be purchased in the online store. This is an extremely limited opportunity to get a late stage Papilio Plus prototype. We have assembled 15 boards and added Spartan 6 LX9 chips to 5 of them. If all five boards sell we will order 10 more chips and complete the remaining boards. Seeed Studio is in the process of manufacturing this same design and we expect they should be available in around 3 months. These boards are not documented and there is not yet support to program the 64Mb SPI Flash chip. Features Papilio One compatible footprint, will support all existing Wings and MegaWingsSpartan 6 LX9 FPGA4Mb ISSI SRAM chip - Can be upgraded to 8 or 16Mb.64Mb Macronix SPI Flash chip which will allow up to 11 Multi-boot bit files.FTDI 2232 - The FPGA has a reset jumper pin to put the FPGA into High-Z so the FTDI chip can be used as a JTAG programmer. Projects like OpenOCD and FlashROM should work, (Not tested yet)32Mhz clock.Reset SwitchUser LED is built onto the board. Version 1.2 Improvements This version 1.2 design is an upgrade to the Papilio One and, in addition, it has some improvements over the Papilio Plus v1.0 design. Alex was kind enough to contribute some changes that make the SRAM implementation better. All SRAM pins are fully routed now. BHE, BLE, and A18 are connected so 8 bit data access is possible and 8 and 16Mb SRAM chips can be fully utilized.The FPGA can be held in a permanent reset allowing the FTDI 2232 chip to be accessed without interference from the FPGA. Jumping JP4 disables the FPGA so the P+ can be used as a JTAG programmer or SPI master. Still a Late Stage Prototype Please be aware that this is still considered a prototype, we have done very extensive testing of the board and it is in the final stage before being considered in production, but it still can see some changes. The biggest concern right now is the SPI Flash chip, I'm not sure if the final product will use something else. These boards are assembled on my Pick and Place machine and have gone through the official Papilio Plus Test Plan, with the exception of the SPI Flash portion. The pricing set here is not necessarily a reflection of what the final pricing will be. These boards have been hand built and all the components have been bought at the full price, no volume discounts mean the component costs are much higher then it will be with the final product. Link to comment Share on other sites More sharing options...
rpflaum Posted March 7, 2012 Report Share Posted March 7, 2012 Jack, Glad to finally be able to purchase one of these to support your ongoing work to support the community! Looking forward to using this enhanced platform to further young student studies in robotics, etc. Bob Link to comment Share on other sites More sharing options...
Jack Gassett Posted March 7, 2012 Author Report Share Posted March 7, 2012 Bob, Thank you very much for your support and patience, I think its been something like six months since I said I would try to put together a batch of these boards. Thank you! Jack. Link to comment Share on other sites More sharing options...
alvieboy Posted March 7, 2012 Report Share Posted March 7, 2012 SPI chip seems to be easy to program. Need help on that ? Link to comment Share on other sites More sharing options...
Jack Gassett Posted March 7, 2012 Author Report Share Posted March 7, 2012 Alvie, I could use some help. I hit my head against a wall for two days on it. The Macronix chip is a MX25L6445E. It works in the same way as the SST chip but I just cannot get it to go into WREN mode. Looking at the datasheet it says that /CS has to go high on the exact boundery of the command or it will be rejected. When I look at the waveform with the Logic Sniffer I can see that /CS goes high at the same time that the clk goes high for the next command. So I think this is what is causing the problem. Unless I'm just missing some other command that needs to be sent and the problem is not with /CS not being on the boundery. I monkeyed around with the MPSSE code a bit to try and change when /CS changes but to fix this is going to require learning much more about the FTDI MPSSE side of things... Unless of course we take a different approach. My thought was to dig into the FlashROM project and possibly adopt that to program the Flash chips. They support many more chips and it will be less headache in the long run. Jack. Link to comment Share on other sites More sharing options...
Guest Rudzz Posted March 8, 2012 Report Share Posted March 8, 2012 Just bought the last one, I think. Excited to get it in my hands, got lots of ideas. I'll definitely be taking a look at that SPI chip when I get it, so if I figure anything out I'll let you know. Link to comment Share on other sites More sharing options...
alvieboy Posted March 8, 2012 Report Share Posted March 8, 2012 When I look at the waveform with the Logic Sniffer I can see that /CS goes high at the same time that the clk goes high for the next command. I don't think this is the issue. Even for other flash (such as SST) the setup time and hold times are required to be at least 5ns. So you ought to have seen this on other chips also. My thought was to dig into the FlashROM project and possibly adopt that to program the Flash chips. They support many more chips and it will be less headache in the long run. Yes, maybe another option. What I can do right now is to use ZPUino to see if we can program it using the serial port. In theory we only need to change the programmer (the bitfiles can be the same). Alvie Link to comment Share on other sites More sharing options...
Jack Gassett Posted March 8, 2012 Author Report Share Posted March 8, 2012 That would be good, I've been a little concerned that I had blinders on and was just fixating on that one little detail. It's the worst when you go through a huge effort to change the whole architecture of how the application works and then that wasn't even the problem. That's one of the reasons I stepped away from it a while. Anyway, it would be good to program it with the ZPUino so I can at least have a working example to go off. It could be that I'm just missing some little command. The SST chip requires a couple commands that the Matronix chip does not implement. I looked for equivalent commands but did not see them. Jack. Link to comment Share on other sites More sharing options...
alvieboy Posted March 8, 2012 Report Share Posted March 8, 2012 Actually this flash looks like a good candidate for the M25P flash driver. So eventually we can try that first. I'll meet you in skype. Álvaro Link to comment Share on other sites More sharing options...
Guest Rudzz Posted March 11, 2012 Report Share Posted March 11, 2012 Is there a ucf file for the Plus yet? I received mine today (super fast shipping), and I got the ucf from hamster's wiki, but I'm trying to figure out what the pin locations are for the led1 and reset button. Link to comment Share on other sites More sharing options...
hamster Posted March 11, 2012 Report Share Posted March 11, 2012 That's a good point... that UCF was for an older prototype... I'll add a note on my wiki... Link to comment Share on other sites More sharing options...
Jack Gassett Posted March 11, 2012 Author Report Share Posted March 11, 2012 Sorry guys, I need to release the source code so you can start playing with these new toys. I've been out of commission for the past couple days with the flu so I haven't released as much info as I wanted to. I'll start getting things together. Jack. Link to comment Share on other sites More sharing options...
Jack Gassett Posted March 11, 2012 Author Report Share Posted March 11, 2012 Ok, I will get everything properly checked into github but for now I wanted to quickly get the design files out there and uploaded a zip file to the forum. Is there a ucf file for the Plus yet? I received mine today (super fast shipping), and I got the ucf from hamster's wiki, but I'm trying to figure out what the pin locations are for the led1 and reset button. This is a newer design then what hamster has so there are some changes in regards to the locations of some memory pins. LED1 is connected to P112 and the reset button is actually connected to program_b so should probably be considered a more destructive reboot of the FPGA then a reset button coming in on a user I/O pin and handled by the HDL would be... Jack. Link to comment Share on other sites More sharing options...
Guest monkeydoo Posted March 16, 2012 Report Share Posted March 16, 2012 How did I miss this?? Has the other batch of 10 been sold yet? No chance of getting a ft232h on these ? Link to comment Share on other sites More sharing options...
Jack Gassett Posted March 19, 2012 Author Report Share Posted March 19, 2012 I'm still waiting for Spartan 6 chips to arrive to make the 10 boards, so there will be a chance to get your hands on one of these boards very soon. Changing to a ft232h is something I've been thinking about, but will require some rework and lots of testing. The other thing to consider is that without more I/O lines there is not much benefit to changing to the ft232h... I might consider updating the Papilio One design (with no SRAM) to use a Spartan 6 and the ft232h design. Then there would be enough I/O to utilize the ft232h. But Papilio Plus is maxed out with I/O usage. Jack. Link to comment Share on other sites More sharing options...
Guest jerryn Posted March 22, 2012 Report Share Posted March 22, 2012 Hi Jack, Do you have any more Papilio Plus Prototypes available ? Link to comment Share on other sites More sharing options...
Jack Gassett Posted March 22, 2012 Author Report Share Posted March 22, 2012 Hello Jerryn, There may be another batch available this next week. I will post here when the batch is ready. Jack. Link to comment Share on other sites More sharing options...
Jack Gassett Posted March 29, 2012 Author Report Share Posted March 29, 2012 Good news, I just finished a second batch of Papilio Plus prototypes and put them up in the store! Jack. Link to comment Share on other sites More sharing options...
Guest monkeydoo Posted March 29, 2012 Report Share Posted March 29, 2012 Got one! I only had USPS standard shipping available. Is there any other method shipping supported to the UK? I didn't hang around and just ordered anyway. Thanks. Link to comment Share on other sites More sharing options...
Jack Gassett Posted March 29, 2012 Author Report Share Posted March 29, 2012 All the other options, Fedex and UPS, cost between $30-60. USPS First Class only costs $7 and includes insurance in case anything goes wrong. In two years I've only had one package not arrive. Occasionally packages will get stuck in customs for a long time but usually they arrive in 7-15 days. If you really want I can enable the other modules, but they are expensive... Jack. Link to comment Share on other sites More sharing options...
Guest monkeydoo Posted March 30, 2012 Report Share Posted March 30, 2012 FedEx Intl. Priority (1-3 days) would be my preference. It's usually around $30 USD to the UK. If there isn't an easy method to invoice me or isn't possible, don't worry. I'll just have to be patient. Link to comment Share on other sites More sharing options...
ben Posted March 30, 2012 Report Share Posted March 30, 2012 Got one! I only had USPS standard shipping available. Is there any other method shipping supported to the UK? I didn't hang around and just ordered anyway. Just the same for me (for France) But standard USPS seems just fine -- I just hope the parcel doesn't get stuck in customs. Link to comment Share on other sites More sharing options...
Guest jheckman Posted April 6, 2012 Report Share Posted April 6, 2012 Should INIT_B, Pin 39, be pulled up to 3v3 for JTAG configuration? Link to comment Share on other sites More sharing options...
Jack Gassett Posted April 6, 2012 Author Report Share Posted April 6, 2012 Hmmm, Interesting point, theoretically if INIT_B is held low at power on it could keep the FPGA disabled. For the Papilio Plus INIT_B is used a generic I/O and is connected to the SRAM chip. At power up the SRAM chip must be providing a 3.3V level which allows it to start up. I'll have to look closer at that. Jack. Link to comment Share on other sites More sharing options...
Guest monkeydoo Posted April 11, 2012 Report Share Posted April 11, 2012 Jack, Board arrived today. Haven't tested yet. Looking forward to playing with it. Cheers Ian Link to comment Share on other sites More sharing options...
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