hamster Posted February 4, 2012 Report Share Posted February 4, 2012 I've written a test bench that simulates the first 32 bytes of the SRAM. It also logs (to the iSim console) if the following occurs: when the write enable pulse is too short when the data setup times for a write is too shortwhen the address bus changes when write enable is activeIt outputs 'X's during the access time, allowing you to see when you capture data before it has settled.Find it at http://hamsterworks.co.nz/mediawiki/index.php/SRAM_testbench Hope it helps somebody Link to comment Share on other sites More sharing options...
alvieboy Posted February 4, 2012 Report Share Posted February 4, 2012 I've been using this one here: http://tams-www.informatik.uni-hamburg.de/vhdl/models/sram/sram.html But it does not support byte accesses. I'll take a look at yours. Alvie Link to comment Share on other sites More sharing options...
hamster Posted February 5, 2012 Author Report Share Posted February 5, 2012 Had a look at that pages you linked to - makes mine look quite primitive! Thanks for the excellent link - things like that very hard to find in Google. You find lots of talk but no code! Link to comment Share on other sites More sharing options...
Recommended Posts
Archived
This topic is now archived and is closed to further replies.