More counters?


Guest shashi

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Guest shashi

Hi Alvaro, Jack et al.,

Would like  to know the possibility of adding some more counters on the ZPUino.    I currently have a student working with me for her M Tech thesis.    We are trying out different options with a Papilio 250.    One of them is to increase the number of 16bit counters.  This is for an astronomical instrument.  (see http://arxiv.org/abs/0912.0076 for a general description of a recent upgrade of the instrument).    8254 counters are being used for counting the digital TTL pulses coming from photomultiplier tubes.  The 8254 is able to count pulses that are a few nanosec wide (pulse remains high for a few ns).  Will the ZPUino's 16bit counter be able to count such pulses?  (We don't have the instrument in the lab right now to test this - it is at the observatory ..)

Thanks in advance for your comments and suggestions,

Best wishes,

Shashi

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Guest gmpundlik

Hi Shashi,

It is possible to add more counters since it is a Wishbone compliant design and there are open source 8253 compatible cores available. In fact you can just instantiate another of the ZPUino's counters at a different address. As for the pulse counting, a regular 8253 is able to count these pulses, the FPGA should definitely be able to do it. In this case I doubt it would be very small, because the best 8253 variant can do 230nS clock high time, that is less than 3MHz.

Anyway, how many nanoseconds are we talking about? A few nanosecond period gets close to GHz rates, which for Spartan3E would be running rather close to its limit. As per datasheets the best it can do is just above 5nS, which is approximately 200MHz at best. The safest bet is working it at 10nS, that is 100 MHz.

If you really require very high speed counting, best way is to develop a specialized counter using minimal entities to reduce the propogation delays as much as possible, maybe tweaking the 8253 model to remove some operation modes and make it a lean and mean design.

Girish

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Hi,

Actually ZPUino is not (yet) wishbone compliant.

Now, regarging the timers you can add as much as you want, most IO space is still free. But remember the two included timers in ZPUino are 16-bit, but they are not able to use an external trigger (however this is rather easy to implement, just tell me if you require it).

In case you want to extend either the number of timers or the resolution that's also very easy to do.

Álvaro

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Guest gmpundlik

Hi Alvie,

Thanks for your reply. I was under the impression that ZPUino is direct derivative of Zylin CPU, and is wishbone compliant.

Anyway, it would be great to add new peripherals to the ZPUino, do you have any help page for that?

Girish

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I was under the impression that ZPUino is direct derivative of Zylin CPU, and is wishbone compliant.

Well, Zylin ZPU is not wishbone compliant either (the small core), but an adaptor exists that allows you to integrate some wishbone devices.

Anyway, it would be great to add new peripherals to the ZPUino, do you have any help page for that?

Not yet :P But I'm planning to write one in the near term. Meanwhile if you want to do it I'll gladly help by email.

Álvaro

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Guest gmpundlik

Hi Alvie,

Thanks for your help. I would like to try these cores put into the ZPUino for initial testing:

http://gadgetforge.gadgetfactory.net/gf/project/stepper_core/

http://gadgetforge.gadgetfactory.net/gf/project/core_led_button/

There is also a ADC core that uses a subset of SPI to read a 1MSPS serial ADC - the SPI ADC wing but it is not ready yet. This is intended to provide analog input interface for any microcontroller transparently, so basically it does not have any specific register set but will emulate the analog register set of target microcontroller.

http://gadgetforge.gadgetfactory.net/gf/project/bpw5011-spiadc/

Out of these Jack has already tested the stepper core and LED/button core is a bit short of the page description, but functional.

It would great to have simple chores like stepper motor control, LED and button interfacing delegated to hardware and have entire CPU bandwith for pure processing. This can greatly reduce the CPU requirements for projects like multi-axis actuators and CNC machines.

A high resolution counter is also a good addition.

I would like to have ZPUino demonstrate the power of FPGA using these custom cores and taking Arduino applications way beyond what they are capable of now.

So if you have some material, even scribblings as to adding custom peripherals to the ZPUino, please do share them with us.

Thanks,

Girish

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There is also a ADC core that uses a subset of SPI to read a 1MSPS serial ADC - the SPI ADC wing but it is not ready yet. This is intended to provide analog input interface for any microcontroller transparently, so basically it does not have any specific register set but will emulate the analog register set of target microcontroller.

ZPUino includes a preliminary ADC controller, with 2Kbyte read buffer. I'm using it for an oscope project, works perfectly well at 500Ksps.

A high resolution counter is also a good addition.

I'll add a "generic" in zpuino_config.vhd to choose the timer resolution.

I would like to have ZPUino demonstrate the power of FPGA using these custom cores and taking Arduino applications way beyond what they are capable of now.

So if you have some material, even scribblings as to adding custom peripherals to the ZPUino, please do share them with us.

I'll mock up a draft document today explaining how to integrate other IO cores. I'll post some news here when it's ready.

Álvaro

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I did a major rewrite to main IO module so that it is easy to connect other peripherals.

I just need to test it and I'll upload to git.

I will also publish ZPUIno Premium, which is a more performable core that current one. Can be up to 7 times faster, depending on operations.

Álvaro

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