Jack Gassett

Papilio "Sump" Logic Analyzer

34 posts in this topic

Hello Gary,

 

This tutorial should walk you through the ins and outs of the best way to use the Papilio as a Logic Analzyer:

http://gadgetfactory.net/learn/2015/07/30/designlab-using-papilio-as-stand-alone-logic-analyzer/

 

Please let me know if there is anything unclear, we will make it better. :)

 

Also, we are working on making the Logic Analyzer even better right now, by providing more memory depth and faster transfer speeds.

 

Jack.

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Hi Jack,

 

   thanks for the reply.

 

I had a little more success this evening. After trying different USB sockets, and setting the baud in the OLS tool to 115200, it started to work, in that I could "Show device metadata". I was able to capture some waveforms but they all looked like squarewaves, so something was wrong. After a few captures the serial connection appeared to break and "Show device metadata" no longer worked (however the TX LED did flash).

 

I was using a level translation wing, and probing around some of the signals looked strange as if there was contention. All rails were very noisy and the 5V rail dipped to 0V. In hindsight I may have plugged the board into the wrong row!

Nevertheless it made me investigate the power supplies. The 5V power from the USB was very low at 4V and the 3.3V was very noisy. Not good. So I found a power supply and used the external power connector. Now all the power rails looked good.

The device now seemed a little more stable, and (after plugging in the wing correctly) I was seeing waveforms. Unforunately the serial connection stopped working, and despite plugging and unplugging the USB I couldn't get it to work again. I'll try it tomorrow after a fresh boot..

 

So progress, and a lesson about taking care plugging into the A/B wing socket, and also a lesson about checking power supplies :) .

 

I've just loaded the latest version of Design Lab, so I'll be trying this out, and I'll be sure to watch the video.

 

regards...

 

--Gary

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Over the weekend I made more progress using the Open Logic Sniffer LA. I also started to find some of the features of the software, which weren't immediately obvious (Or apparently documents in the Wiki).

I have been using it to debug some old hardware of a 32 bit uP circuit (NS32016). I was able to find the bug in the boot loader software, even though I initially thought that there was a hardware problem.

 

I googled for 16 bit LAs and was shocked at the price. 32 bit LAs seem thin on the ground. So the Papilio with wings really is a great cost effective solution.

 

Unfortunately I am still having problems with the USB locking up. Once it gets into the mode where the Papilio isn't seen by the USB, it is difficult to get it working again. Re-powering the Papilio and unplugging and re-plugging the USB didn't always work. After many minutes of messing around it finally started working again.

 

I was going to upload a screen shot, but It's not clear that this is possible.

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Hello Papry,

 

I'm glad to hear that you are happy with the overall solution. I'm worried about the USB locking up though... Is this under Windows? Which version? Let's keep on top of this and see if we can find a solution...

 

Jack.

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OK Jack,

 

    having found the software bug I haven't really used the Logic Analyser much, however I have used ISE to compile the Papilio One OLS sources (which went reasonably pain free), and then port the code to the Papilio Pro (which went much better once I deleted the old memory and DCM modules, and re-made them). Afterwards I also found a posting from someone who had also ported the OLS source to the Papilio Pro. I confirm that the hardware is good for 100MHz, but fails 200MHz timing by quite a margin (for both One and Pro). My intention is to see if the communications with the Papilio Pro are any more reliable, but it is a useful exercise to re-familiarise myself with ISE.

 

FYI, I use Windows7 64-bit. I am using a USB3 connection on the front panel, which then has an extender to reach the board. So the total cable length from the motherboard could be a couple of metres.

 

regards...

 

--Gary

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The recent session using the Papilio  Pro went much better, in that I didn't suffer any USB/COMM port disconnects.

It was really great to have 32 channels for debugging a 16 bit databus processor. I was able to track down a bug in my assembler that makes any long absolute jump actually go to zero which is the reset start address!

The OLS client is really impressive, but there are some minor faults. For example when displaying groups of pins (in hex) if they are higher order channels it adds zeroes at the bottom for channels 0-7 or 0,7 and 0-15, making the text field longer.

Pity that development appears to have really slowed down, as it is really close to being brilliant.

 

--Gary

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Hi,

>> Pity that development appears to have really slowed down, as it is really close to being brilliant.

the disclaimer first, I'm using SUMP only with the Pipistrello board, where I have it in flash ROM. This keeps the Papilio board free for "higher risk" stuff :-)

Anyway: If I had to do serious work with the logic analyzer, the first thing I'd do is hijack the interface code and then write a very simple command line back-end that sets trigger conditions, start an acquisition, then dumps everything to .vcd (the file format is trivial BTW) so that it can be analyzed in GTKwave later.

My $0.02... So far I've been lucky to get the complex issues sorted out in simulation, the logic analyzer is more like a swiss army knife (which does save the day, occasionally).

 

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On 1/30/2017 at 1:45 AM, offroad said:

Hi,

>> Pity that development appears to have really slowed down, as it is really close to being brilliant.

the disclaimer first, I'm using SUMP only with the Pipistrello board, where I have it in flash ROM. This keeps the Papilio board free for "higher risk" stuff :-)

Anyway: If I had to do serious work with the logic analyzer, the first thing I'd do is hijack the interface code and then write a very simple command line back-end that sets trigger conditions, start an acquisition, then dumps everything to .vcd (the file format is trivial BTW) so that it can be analyzed in GTKwave later.

My $0.02... So far I've been lucky to get the complex issues sorted out in simulation, the logic analyzer is more like a swiss army knife (which does save the day, occasionally).

 

Are there any command line tools or example code to setup advanced triggers?  The only program I've found that supports the advanced trigger is a Windows executable which doesn't help me since I'm running Linux.

Skip

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It might be the easiest to write it yourself. From how I understand it (disclaimer - I never actually hacked it) it boils down to write a few bytes to a UART.

See this link at "Long commands".

At first glance the trigger section looks exactly like what's available in the GUI.

As a personal comment: I've learned programming on Unix and often feel sorry for those folks who know only Microsoft GUI-driven madness. But, for FPGAs the additional burden from running Linux is too much for a hobbyist, IMHO. I'd pick my battles carefully... (and PS: In Windows C#, the minimal program to open a serial port, write some bytes, pick some output bytes will probably fit on one screen or two. It's extremely usable for this kind of job).

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