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Found 27 results

  1. Hi everyone, I have a papilio pro working successfully with designlab but I want to use a custom board (like papilio one) with it. I've selected papilio one 250k and "Load circuit" seems to be ok, but when I tried to upload... the output is attached: "Cannot get programmer version, aborting". I've checked COM port, FTDI configuration EEPROM is empty (with FT_prog), papilio drivers are loaded... I also tried to change some values in the FPGA (HSWAP is '0' so every pin will be pullup, but I've pulled up M0 and M2, and M1 to GND. Also "Done" and "init b" pulled up.)... Any help? My XC3S250E has different IDCODE so I've added this line to the devlist.txt file: Papilio-prog seems to work good. What is the problem? Thanks
  2. hi, i'm using designlab 1.0.8 with ise 14.7 on ubuntu 17.04 amd64, targeting a papilio pro/spartan 6 with the zpuino soft processor. i've got a working proof-of-concept design which combines a few bits and pieces, namely the whirlyfly (whirlygig) random number generator (https://github.com/zdavkeos/whirlyfly), a couple wishbone uart's (COMM_zpuino_wb_UART.vhd), and a wishbone watchdog peripheral written in verilog that i've been trying to integrate (https://github.com/freecores/watchdog/tree/master/rtl/verilog). the rng and uart components appear to be working fine, giving me up to 280KB/s or so of random data when polling both wishbone uart's sequentially at 3mbit/s. i'm then using the reference blake2s hash implementation (https://github.com/mjosaarinen/blake2_mjosref) to further "whiten" the output of the rng's. this slows down the output to about 30KB/s which is fine considering it's a complex operation. that's not the issue. anyhow, the wishbone peripherals included in designlab, as well as the schematic representation of the zpuino 2.0 soft processor bundle the input and output wires into the wishbone_in/wishbone_out connections, which i assume is for simplicity when placing components using the schematic editor in ise. the watchdog.v implementation linked previously is designed with all of the wishbone wires broken out like: module watchdog(wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_int_o); i've been trying unsuccessfully now for a while to modify the watchdog.v to present the same interface, so i can easily attach it to the zpuino using the schematic editor gui (i.e. Papilio_Pro.sch) in ise. without knowing how to modify the schematic symbol after generating it, i just took the one from the wishbone uart included in designlab, replaced the relevant variables and removed the tx/rx, and overwrote the existing watchdog.sym in the project directory. that seemed to work fine and let me drag & drop the watchdog onto an open wishbone port on the zpuino. the issue i'm having is that i can't seem to get the pre-synthesis rtl schematic viewer in planahead to "alias" the slices of wishbone_in/wishbone_out to the friendly-named wires representative of their function within the wishbone bus (e.g. wire [31:0] wb_dat_i; assign wb_dat_i [31:0] = wishbone_in [59:28];). the design does synthesize fine, but i haven't bothered trying to write C code for the zpuino to interface/write with the watchdog peripheral because of the apparent brokenness being shown in planahead. here's a simplification of what i've been doing unsuccessfully to create the "friendly" aliases of wishbone_in/wishbone_out: // original, simplified module watchdog(wb_clk_i, wb_rst_i, wb_dat_i, ...); parameter Tp = 1; input wb_clk_i; input wb_rst_i; input [`WDT_WIDTH - 1:0] wb_dat_i; ... // new, simplified module watchdog(wishbone_in, wishbone_out); parameter Tp = 1; input [100:0] wishbone_in; output [100:0] wishbone_out; wire wb_clk_i = wishbone_in [61]; wire wb_rst_i = wishbone_in [60]; wire [31:0] wb_dat_i; assign wb_dat_i [31:0] = wishbone_in [59:28]; ... // mutual code between original & new ... always @(posedge wb_rst_i or posedge wb_clk_i) if (wb_rst_i) begin stb <= #Tp 1'b0; we <= #Tp 1'b0; dat_ir <= #Tp `WDT_WIDTH'h0; end else begin stb <= #Tp wb_stb_i && wb_cyc_i; we <= #Tp wb_we_i; dat_ir <= #Tp wb_dat_i; end ... attached are abridged screenshots of what planahead shows for the unmodified verilog code straight from the aforementioned github repo (top image), and the seemingly broken output from my modified version where i try to bundle up the wires into wishbone_in/wishbone_out. the dat_ir is where wb_dat_i is showing a single wire instead of [31:0]. also attached is the work-in-progress modified watchdog.v. please keep in mind that these are the first lines of vhdl/verilog i've ever written so my knowledge of syntax/terminology is very limited. thanks! watchdog.v
  3. dcachev2_zpuino_preliminar.tar.gz

    Version 2.0.0

    25 downloads

    Preliminary ZPUino dcache (v2)
  4. ZPUino HDL Source Code

    Version 1.0

    7,963 downloads

    ZPUino Soft Processor Source Code, use this to synthesize your own custom versions of the ZPUino Soft Processor with the peripherals that you want! Quick Links: ZPUino Home Page ZPUino User Guide for use with Papilio
  5. Dear Altruists, I'm new to Papilio Pro FPGA. I designed my circuit with VHDL and also synthesized it, and it is ready to be loaded in the papilio pro fpga. My circuits interface has an input of 64 bits and output of 1 bit. I need only to send this 64 bit data from my pc to FPGA and receive the output of 1 bit ( please check the uploaded circuit interface). I already watched most of the learning videos. I have already contacted Mr. Alvie and thanks to him he reply with an answer, but it was a little difficult for me to understand as I am new to FPGA. His answer was that I should connect my circuits to one of wishbone ZPUino slots, and use ZPUino to interface with the USB/serial using software moving data to and form my circuits. However, the things that I don't understand are that: 1. Should i connect my circuits to wishbone bridge and then connect my circuits to the wishbone slots as you did here ( http://gadgetfactory.net/learn/2015/05/14/designlab-libraries-make-a-wishbone-library-2/). If the answer yes, should I connect the the both input and output to the wishbone bridge. If answer no, then should I interface my circuits directly to the ZPUino wishbone slots. 2. If I connect my circuits to ZPUino wishbone slots. The input 64 bits and the output 1 bit should be connected to what to the slots or Paplilio Pro Pins. 3. Mr. Jack illustrate in the learning site videos that ZPUino should be loaded to the SPI not to the FPGA Spartan6. So, If I am going to interface my design to ZPUino how can I load the circuits to the FPGA. 4. If I am going to make an interface of the UART I think I just need to follow as same as Mr. Jack did in this video( http://gadgetfactory.net/learn/2013/11/15/papilio-schematic-library-10-serial-ports/ ) Please forgive my shortcomings. I am new to these things. Any help will be highly appreciated. Thanks
  6. external interrupt

    I am trying to use an external interrupt on the ZPUino to report status of an 8-bit counter via the USB port. I have the code working on a Arduino Mega. I want to port the code over to a Papilio One 250 and utilize the FPGA to handle some external output signals. Basically I am looking for the equivalent to the following Arduino code: attachInterrupt(0, capture_bearing, RISING); Any help would be greatly appreciated.
  7. I recently purchased a Papilio Pro together with a Logic Start board. Whenever I try to send a compiled example program to the board I get the following error message; Board: GadgetFactory Papilio Pro LX9 @ 96000000 Hz (0xa4041700) Board mismatch!!!. Board is: 0xa4041700 'GadgetFactory Papilio Pro LX9' Sketch is for: 0xb4041700 'GadgetFactory Papilio Pro LX9 (ZPUino 2.0)' My conclusion is that the supplied board has version 1 of the ZPUino installed and not the latest version as I would have expected. How do I install ZPUino version 2.0.
  8. Hi, I know that in general the configuration memory of FPGAs can be accessed and used with some limitations. And as the ZPUino loads it's program from the FLASH I would be very interested to know if it's possible to store and read some values from the sketch? Thanks, Tobias
  9. Hi, First of all: I started working with my Papilio Pro again and I really like how things developed here! I really like the DesignLab and how easy it easy to connect things to your own blocks! Thanks. To verify some custom hardware connected to the board I need to create some square wave signal with some MHz. As neither analogWrite nor the PWM functions in the Timer class are working / present I tried writing to the registers directly (inspired by some forum post here) also does not toggle the PIN (WB12): #include "register.h" #define FREQUENCY 100000#define SW1 WB12void setup(){ pinMode(SW1, OUTPUT); pinModePPS(SW1, HIGH); outputPinForFunction(SW1, IOPIN_TIMER0_OC); TMR0CNT = 0; TMR0CMP = (CLK_FREQ / FREQUENCY) - 1; TMR0CTL = _BV(TCTLENA)|_BV(TCTLDIR)|_BV(TCTLCCM); TMR0PWMLOW(0) = 0; TMR0PWMHIGH(0) = 200; TMR0PWMCTL(0) = 1;} But for now the pin stays low...
  10. Is it possible to add more Wishbone Slots to the ZPUino?
  11. hi there, im new to the forum. i am playing around with the zpuino for about a month now in zap and vhdl. it runs on the papilio pro. the papilio 250k is nice as well, but its too small for my project. mainly i like it, because i needed 8 serial ports for my project. so far everything works just fine! :-) the 8 serial ports & spi work as expected. as my project gets bigger, i was wondering, if there is a port for freertos available, which ive used before on stm32-mcus. ideally i could do with a freertos-version within the zap-ide. the only thing i spotted on the net is this on here: https://github.com/alvieboy/ZPUino-HDL/tree/master/zpu/sw/freertos unfortunately the freertos-files are not included. im using freertos 7.52 and in the path i can't find the zpu-folder. can anybody advise me in regards to freertos on the zpuino ? best regards, mOnO Edit: its not included in FreeRTOS V5.30. its also not included in the current FreeRTOS 8.12...
  12. Hi guys, Yes, it's true, the ZPUino project is really needing your help. Your help as users, because all we do is for the users benefit, and sometimes we just don't have the required free time to accomplish all we thing users need, but also because since we are not real users, we fail to see what real ones expect from the platform. Business as usual Anyway, A lot of improvements for ZPUino are being polished as I write. The one that will have more impact is an instruction cache. This instruction cache is now perfectly stabilized, and ready for mainstream. And you might ask: how come an instruction cache is so important and has that much impact ? Well, it's actually quite simple. ZPUino requires a constant feed of instructions, in order to attain its maximum performance. As of now we use internal FPGA block rams, and things go smooth because they are a 1-cycle read. BUT, if you want to use external memory (SRAM, SDRAM, DDR), the latencies are sooo high to fetch a single byte from it that ZPU ends up idling all the time. So, in order to properly use external memories, the instruction cache was implemented - it works perfectly with all three memory types stated above. So, with instruction cache, we can actually use external memory now - and this is a huge improvement. Note that external memory is used for *both* instruction and data, unlike Arduino, which imposes distinct limits on code and data. Just sum your code and data, and see if it fits (btw, upcoming IDE will do that for you). Second feature, which is aimed at internal memory devices, is a ZX Spectrum compatible graphical adaptor. It's so small that you can even use a Papilio One 250 to build applications and games. And this second feature is indeed where we want your help. We need help with documentation, and help with a new demo we are working on - all to be ran on a Papilio One 250 (you can use another board if you feel like). So, if you like coding, and want to help with code itself or documentation, drop us a note at zpuino@alvie.com. We will provide you everything you need to contribute. Right now, we have a game almost ready for testing, but we do want *you* to improve it before others can see it and enjoy. So, if you know "C++" (arduino-style) and wish to help, please contact us. You will of course be mentioned as a co-author, and eventually other benefits. We are also planning a full-color, full-resolution graphical adaptor for Papilio Pro. But let's go step by step Best, Alvie
  13. Although current ZPUino timers implement a very complex and capable PWM system, we are struggling a bit to integrate PWM and Timer support at same time in ZPUino code. It's rather hard to mix both in a sensible way, because timers can have been claimed for other modules, and PWM may not always be able to map the correct pin, or map the correct timer, and fixing this in software will end up with a bit mess of code and bugs. So, after a quick chat with Jack a few days ago, we concluded that it would be better to have a separate PWM module from now on. But we are not entirely sure of what you users may need/want from such a module. I have spent last couple of days thinking about this, and I have come to a preliminary design which I'd like you to comment on. This design is based on my previous experience with a very PWM-capable generator - the Texas Instruments TMS320F series. I have borrowed some ideas from them, and my plan is roughly to have something like this (I have already implemented most of it, actually): -- Overall Module view - 16-bit counter, 8-bit prescaler. Up to 4 PWM compare/output blocks. - Each output block has 2 outputs. - Sync-in/Sync-out support for cascading more modules (if for example different timebases are needed) and to keep them perfectly synchronized. - Interrupt support. - Clocking block - 8-bit prescaler. Can divide the main clock by anything from 1 to 255. - Only meant to be programmed once. Subsequent programming may lead to glitches. - Per-module clock enable/disable. - Counter block - Three modes: count-up, count-down, and count-up-down - 16-bit period, with shadow register configurable. Phase counter for sync-in. - Compare block (up to 4 blocks per module) - 2 comparators (A and with 16-bit comparator. - Shadowing support - Output module (up to 4 blocks per module) - 2 outputs. - Each output configurable to both A/B comparators, zero or overflow. Can either set, clear, toggle or no-op on output pin. Comments ? Alvie
  14. Hi All, I've been getting back into some Papilio development again lately and have been very happy to see all the improvements to the SoC ecosystem. I've been able to reproduce the pwn tutorial (very helpful!) and now want to add a toy 'adder' (add two registers and store the result in a third) component. I'm struggling to understand the behavior of async vs sync from the perspective of software running on zpuino. With an async result do you poll for a ready bit, vs having the cpu block on sync? Are there software examples of the two, or best practices to follow? The default template is async, and the vhdl code makes sense, I'm just wondering… for the adder component described above, should I be using sync? (I've seen the examples of that in another thread). Thanks in advance, -Greg
  15. Hello, I'm also getting the "Cannot get programmer version, aborting" message when trying to upload a sketch to my Pro. I've tried the suggestions provided to others but continually get the same message. To date I've tried the following with no luck: - Ensuring that I have the correct port selected (tried again after removing every last trace of FTDI software from my Win7 pc). - Changing cables and ports on my pc. - The Zap 2.2.0 IDE bootloader approach as well as the approach described in the "LogicStart MegaWing Example" sketch. - Looking at it sternly to try and guilt it into working. - Ensured that Papillio Programmer is selected as the programmer. - Tried each of the Pro LX9 ZPUino boards when burning the bootloader and trying to upload code. I can see the TX light flashing when I try to upload and, as the others have stated, the AVR quickstart works just fine so I'm at a loss. My environment is Win7-64, Zap IDE 2.2.0, Loader 2.6 and the board says "BPC3011 V1.3". Any suggestions? Thanks, David
  16. Hello, Which app to use to save PNG file and then convert it with png2zpuinohqvga tool to get correct image ? Given example works, but not my own (getting random colors). I can't find information about image size and colors count, too. Thanks
  17. Hello, I am the new owner of a Papilio 500 with a Logic Start Mega Wing. I am eager to dig into the VGA and sound capabilities. I have taken the following steps and am bumping up against a "Cannot get programmer version, aborting" error when trying to upload the VGA Hello World example. From the top: Download Papilio Boot Loader Run the Erase and Verify operations in the Papilio Boot Loader. Download ZAP 2.2.0 Set the Board to the Papilio One 500 running the Mega Start Hyperion... Select the Papilio Programmer Burn the Bootloader Upload the VGA Hello WorldI would expect the program to upload but I get the following output: Executing C:\Users\brent\Desktop\papilio-zap-ide/hardware/tools/zpu/bin/zpu-elf-size C:\Users\brent\AppData\Local\Temp\build1289722314899768199.tmp/Hello_World.cpp.elfBinary sketch size: 2,036 bytes (of a 12,160 byte maximum) - 1,992 bytes ROM, 52 bytes memory, 16% usedCannot get programmer version, aborting Any thoughts on how to get around this issue?
  18. Just like to share with you guys an overview of a typical block transfer from the SDRAM. This is used by the ZPUino instruction cache and (for version 2) also the DMA channel. This goes as fast as possible can go. The wishbone data interface witdh is 32-bit, and the SDRAM is 16-bit, so it takes 2 cycles to grab the whole 32-bit word from the SDRAM. In this image we can see the wishbone starting a cycle (asserting the CYC signal), and strobing an address (by asserting the STB signal). If you look more clearly (you cannot see the whole address value here), right after strobing the first address, the STALL signal from the sdram controller is asserted. At this point, the system already has a new address on the bus, and will hold it there until the STALL signal from the controller goes low again. It then proceeds to the next address. This up to the point that there are no more addresses to place on the bus, where the master lowers the STB signal, but it keeps the CYC signal on. Right after the first address strobe, the SDRAM starts to receive the requests. They are also bursted, so you see that addresses are changing even before the first reply from the SDRAM (just after the first high-z period, the longer one on the DQ line). Again, we pipeline even at the SDRAM level, not only at the wishbone level. When the first data starts to come out, you can see the ACK signal from the controller, signaling that data is valid. We keep on getting an ACK each 2 clock cycles until we have read everything we bursted into the SDRAM controller, after which the master lowers the CYC signal, relinquishing the SDRAM for other masters that may exist. A closer look: Here you can see the start of the transaction, with the proper values filled in. Notice how the clock and the SDRAM lines are not aligned: this takes all the IO delays into account. Alvie
  19. Hello, I was wondering if anyone could point me in the right direction on a problem I am having. I am trying to understand the ZPUino system and I want to make a customized core for my project so I am trying to just figure out how the whole project source fits together. I can compile a with whatever core changes I intend on making bit successfully. There is a bootloader section in the repository which has debug and verbose options. I am attempting to just enable verbose options as an exercise in understanding how all the pieces fit together. I can build the bootloader code successfully I have searched but I cant seem to find any information on how to integrate a custom bootloader with a custom core. In a previous post i read that the ZPUino doesnt use a bmm file so how do you integrate the bit with the hex of the bootloader. Could anyone point me in the right direction. Thanks
  20. I'm using Ubuntu 13.04 64-bit and I noticed that the ZPUino IDE came with "zpu_tools_linux32.tar.bz". I tried to use these on my machine, but I got a "No such file or directory" error. I did a google search and saw this: http://askubuntu.com/questions/133389/no-such-file-or-directory-but-the-file-exists Which has made me think I must compile the ZPU toolchain for a 64-bit machine. I follow the steps as directed by this page: http://opensource.zylin.com/zpudownload.html I run into this error: *** buffer overflow detected ***: zpu-elf-ar terminated======= Backtrace: =========/lib/x86_64-linux-gnu/libc.so.6(__fortify_fail+0x5c)[0x2aaaaade15cc]/lib/x86_64-linux-gnu/libc.so.6(+0x110560)[0x2aaaaade0560]/lib/x86_64-linux-gnu/libc.so.6(+0x10f9e9)[0x2aaaaaddf9e9]/lib/x86_64-linux-gnu/libc.so.6(_IO_default_xsputn+0xdb)[0x2aaaaad4caeb]/lib/x86_64-linux-gnu/libc.so.6(_IO_padn+0xf0)[0x2aaaaad40720]/lib/x86_64-linux-gnu/libc.so.6(_IO_vfprintf+0x4638)[0x2aaaaad1de68]/lib/x86_64-linux-gnu/libc.so.6(__vsprintf_chk+0x94)[0x2aaaaaddfa84]/lib/x86_64-linux-gnu/libc.so.6(__sprintf_chk+0x7d)[0x2aaaaaddf9cd]zpu-elf-ar[0x4072cd]zpu-elf-ar[0x4091ff]zpu-elf-ar[0x40cda7]zpu-elf-ar[0x40494b]zpu-elf-ar[0x404f07]zpu-elf-ar[0x40274b]/lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0xf5)[0x2aaaaacf1ea5]zpu-elf-ar[0x402a95]======= Memory map: ========00400000-00452000 r-xp 00000000 08:02 12724355 /home/kwoods/workspace/ZPU/zpugcc/toolchain/install/bin/zpu-elf-ar00652000-00653000 r--p 00052000 08:02 12724355 /home/kwoods/workspace/ZPU/zpugcc/toolchain/install/bin/zpu-elf-ar00653000-00654000 rw-p 00053000 08:02 12724355 /home/kwoods/workspace/ZPU/zpugcc/toolchain/install/bin/zpu-elf-ar00654000-00658000 rw-p 00000000 00:00 0 0162e000-01736000 rw-p 00000000 00:00 0 [heap]2aaaaaaab000-2aaaaaace000 r-xp 00000000 08:02 11013730 /lib/x86_64-linux-gnu/ld-2.17.so2aaaaaace000-2aaaaaad0000 rw-p 00000000 00:00 0 2aaaaaad0000-2aaaaaad7000 r--s 00000000 08:02 787339 /usr/lib/x86_64-linux-gnu/gconv/gconv-modules.cache2aaaaaad7000-2aaaaaad8000 rw-p 00000000 00:00 0 2aaaaaae4000-2aaaaaae7000 rw-p 00000000 00:00 0 2aaaaaccd000-2aaaaacce000 r--p 00022000 08:02 11013730 /lib/x86_64-linux-gnu/ld-2.17.so2aaaaacce000-2aaaaacd0000 rw-p 00023000 08:02 11013730 /lib/x86_64-linux-gnu/ld-2.17.so2aaaaacd0000-2aaaaae8e000 r-xp 00000000 08:02 11013754 /lib/x86_64-linux-gnu/libc-2.17.so2aaaaae8e000-2aaaab08d000 ---p 001be000 08:02 11013754 /lib/x86_64-linux-gnu/libc-2.17.so2aaaab08d000-2aaaab091000 r--p 001bd000 08:02 11013754 /lib/x86_64-linux-gnu/libc-2.17.so2aaaab091000-2aaaab093000 rw-p 001c1000 08:02 11013754 /lib/x86_64-linux-gnu/libc-2.17.so2aaaab093000-2aaaab098000 rw-p 00000000 00:00 0 2aaaab098000-2aaaab779000 r--p 00000000 08:02 399404 /usr/lib/locale/locale-archive2aaaab779000-2aaaab78d000 r-xp 00000000 08:02 11013779 /lib/x86_64-linux-gnu/libgcc_s.so.12aaaab78d000-2aaaab98d000 ---p 00014000 08:02 11013779 /lib/x86_64-linux-gnu/libgcc_s.so.12aaaab98d000-2aaaab98e000 r--p 00014000 08:02 11013779 /lib/x86_64-linux-gnu/libgcc_s.so.12aaaab98e000-2aaaab98f000 rw-p 00015000 08:02 11013779 /lib/x86_64-linux-gnu/libgcc_s.so.17fff2233d000-7fff22360000 rw-p 00000000 00:00 0 [stack]7fff223fe000-7fff22400000 r-xp 00000000 00:00 0 [vdso]ffffffffff600000-ffffffffff601000 r-xp 00000000 00:00 0 [vsyscall]make[2]: *** [libgcc.a] Aborted (core dumped)make[2]: *** Deleting file `libgcc.a'make[2]: Leaving directory `/home/kwoods/workspace/ZPU/zpugcc/toolchain/gccbuild/gcc'make[1]: *** [stmp-multilib] Error 2make[1]: Leaving directory `/home/kwoods/workspace/ZPU/zpugcc/toolchain/gccbuild/gcc'make: *** [all-gcc] Error 2Is there any way to get around this? I'm a bit stuck and my end goal right now is just to get the ZPUino IDE to work. Also, is there any chance a simplified version of Linux could be compiled with the ZPU toolchain?
  21. Hi - I have a need to add additional logic to the ZPUino-HDL project. To start I just try to compile the existing system and load it. This fails miserably. Here are my findings thus far: 1) The Makefile in the papilio-pro directory of the boards does not work with the 'standard' installation from Xilinx. It appears to rely on having mingw, or some other installation available. If I change the Makefile to use 'mkdir.exe' and 'rm.exe' then I am at least able to issue 'make' and 'make clean' (though 'clean' doesn't actually do anything due to differences in the specification of the file expansion). 2) The compilation completes, but the .map file does not match that in the repository (other than expected differences, like times, etc). There are some differences in the number of slices used and flip-flop counts. 3) Even though the compilation completes it will not execute when the .bit file is renamed and moved into the 'bitstreams' directory of the aruino-1.5. I believe that this is due to a bad .bmm file. I have tried to recreate a .bmm file, but there are many more BRAM16 (and one BRAM8) placements in the resultant output than are called out for in the .bmm file. So, how can I recompile the ZPUino-HDL to generate the .bit file for use in the arduino environment? Perhaps there are files that are not checked into the repository, as .gitignore is pretty extensive? Thanks, Richard
  22. Beyond the various new features per the wiki page, how does the Papilio Pro stack up to the One (500K) in terms of its capacity to contain a given logic design, particularly the Arduino and ZPUino cores? My point of reference is this spec sheet. The One's XC3S500E appears to have far more slices compared to the Pro's XC6SLX9 (even when considering the 2:1(?) difference in slice sizes between the newer Spartan-6 and the older Spartan-3), but of course there's the new DSPs and such as well in the 6. Other than that, the Spartan-6 seems to have slightly fewer logic cells and slightly more flip-flops (but do those numbers include what's in the slices, etc.?) Thanks in advance, and if this is all covered elsewhere already just let me know... so far I haven't stumbled upon a head-to-head comparison of the Pro vs the One 500K with these details, and that'd be useful info for people switching to the Pro (or, like me, starting out with it).
  23. Hi all. I'm enjoying learning VHDL but thought I'd have a look at the Zpuino environment as I have a Papilio 500 and logicstart board. On the http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/logicstart-megawing/zpuino-test-code-for-the-logicstart-megawing-r64 page. The link to the bitfile doesn't allow me access. I get permission denied. Is that because I am unworthy or is the bitfile somewhere else? Just thought I'd mention.. cheers, Steve.
  24. A while back I asked Alvie if he had any easy to understand templates for a wishbone peripheral that could be plugged into the ZPUino. He quickly threw together four examples and sent them to me but I never got a chance to do anything with them. I was just looking them over today when I realized I should probably post these to the forums so everyone can enjoy them! So here goes: Example 1 -- This example uses asynchronous outputs.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.numeric_std.all;entity example1 is port ( wb_clk_i: in std_logic; -- Wishbone clock wb_rst_i: in std_logic; -- Wishbone reset (synchronous) wb_dat_o: out std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) wb_dat_i: in std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) wb_adr_i: in std_logic_vector(31 downto 2); -- Wishbone address input (30 bits) wb_we_i: in std_logic; -- Wishbone write enable signal wb_cyc_i: in std_logic; -- Wishbone cycle signal wb_stb_i: in std_logic; -- Wishbone strobe signal wb_ack_o: out std_logic -- Wishbone acknowledge out signal );end entity example1;architecture rtl of example1 is signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits) signal register2: std_logic_vector(31 downto 0); -- Register 2 (32 bits) signal register3: std_logic_vector(7 downto 0); -- Register 3 (8 bits)begin -- Asynchronous acknowledge wb_ack_o <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0'; -- Multiplex the data output (asynchronous) process(register1,register2,register3, wb_adr_i) begin -- Multiplex the read depending on the address. Use only the 2 lowest bits of addr case wb_adr_i(3 downto 2) is when "00" => wb_dat_o <= register1; -- Output register1 when "01" => wb_dat_o <= register2; -- Output register2 when "10" => wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero wb_dat_o(7 downto 0) <= register3; -- since register3 only has 8 bits when others => wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses end case; end process; process(wb_clk_i) begin if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock if wb_rst_i='1' then -- Reset request, put register1 and register2 with zeroes, -- put register 3 with binary 10101010b register1 <= (others => '0'); register2 <= (others => '0'); register3 <= "10101010"; else -- Not reset -- Check if someone is writing if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then -- Yes, its a write. See for which register based on address case wb_adr_i(3 downto 2) is when "00" => register1 <= wb_dat_i; -- Set register1 when "01" => register2 <= wb_dat_i; -- Set register2 when "10" => register3 <= wb_dat_i(7 downto 0); -- Only lower 8 bits for register3 when others => null; -- Nothing to do for other addresses end case; end if; end if; end if; end process;end rtl;Example 2 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.numeric_std.all;entity example2 is port ( wb_clk_i: in std_logic; -- Wishbone clock wb_rst_i: in std_logic; -- Wishbone reset (synchronous) wb_dat_o: out std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) wb_dat_i: in std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) wb_adr_i: in std_logic_vector(31 downto 2); -- Wishbone address input (30 bits) wb_we_i: in std_logic; -- Wishbone write enable signal wb_cyc_i: in std_logic; -- Wishbone cycle signal wb_stb_i: in std_logic; -- Wishbone strobe signal wb_ack_o: out std_logic -- Wishbone acknowledge out signal );end entity example2;architecture rtl of example2 is signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits) signal register2: std_logic_vector(31 downto 0); -- Register 2 (32 bits) signal register3: std_logic_vector(7 downto 0); -- Register 3 (8 bits) signal ack_i: std_logic; -- Internal ACK signal (flip flop)begin -- This example uses fully synchronous outputs. wb_ack_o <= ack_i; -- Tie ACK output to our flip flop process(wb_clk_i) begin if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock -- Always set output data on rising edge, even if reset is set. case wb_adr_i(3 downto 2) is when "00" => wb_dat_o <= register1; -- Output register1 when "01" => wb_dat_o <= register2; -- Output register2 when "10" => wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero wb_dat_o(7 downto 0) <= register3; -- since register3 only has 8 bits when others => wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses end case; ack_i <= '0'; -- Reset ACK value by default if wb_rst_i='1' then -- Reset request, put register1 and register2 with zeroes, -- put register 3 with binary 10101010b register1 <= (others => '0'); register2 <= (others => '0'); register3 <= "10101010"; else -- Not reset -- See if we did not acknowledged a cycle, otherwise we need to ignore -- the apparent request, because wishbone signals are still set if ack_i='0' then -- Check if someone is accessing if wb_cyc_i='1' and wb_stb_i='1' then ack_i<='1'; -- Acknowledge the read/write. Actual read data was set above. if wb_we_i='1' then -- Its a write. See for which register based on address case wb_adr_i(3 downto 2) is when "00" => register1 <= wb_dat_i; -- Set register1 when "01" => register2 <= wb_dat_i; -- Set register2 when "10" => register3 <= wb_dat_i(7 downto 0); -- Only lower 8 bits for register3 when others => null; -- Nothing to do for other addresses end case; end if; -- if wb_we_i='1' end if; -- if wb_cyc_i='1' and wb_stb_i='1' end if; -- if ack_i='0' end if; -- if wb_rst_i='1' end if; -- if rising_edge(wb_clk_i) end process;end rtl;Example 3 -- This example uses fully synchronous outputs and record-based registerslibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.numeric_std.all;entity example3 is port ( wb_clk_i: in std_logic; -- Wishbone clock wb_rst_i: in std_logic; -- Wishbone reset (synchronous) wb_dat_o: out std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) wb_dat_i: in std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) wb_adr_i: in std_logic_vector(31 downto 2); -- Wishbone address input (30 bits) wb_we_i: in std_logic; -- Wishbone write enable signal wb_cyc_i: in std_logic; -- Wishbone cycle signal wb_stb_i: in std_logic; -- Wishbone strobe signal wb_ack_o: out std_logic -- Wishbone acknowledge out signal );end entity example3;architecture rtl of example3 is type regstype is record register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits) register2: std_logic_vector(31 downto 0); -- Register 2 (32 bits) register3: std_logic_vector(7 downto 0); -- Register 3 (8 bits) ack: std_logic; -- Ack signal to output (register/ff) dat: std_logic_vector(31 downto 0); -- Data out register/ff end record; signal r: regstype; -- Main registersbegin wb_ack_o <= r.ack; -- Tie ACK output to our flip flop wb_dat_o <= r.dat; -- And data out also -- This is a single process, with mixed asynchronous and synchronous parts process(wb_adr_i,wb_dat_i,wb_clk_i,wb_cyc_i,wb_stb_i,wb_we_i,wb_rst_i,r) variable v: regstype; -- Local variable with register values begin v := r; -- Set v with our saved regs. We use 'v' to write, and 'r' to read -- Always set output data on rising edge, even if reset is set. case wb_adr_i(3 downto 2) is when "00" => v.dat := r.register1; -- Output register1 when "01" => v.dat := r.register2; -- Output register2 when "10" => v.dat(31 downto 0) := (others => '0'); -- We put all upper 24 bits to zero v.dat(7 downto 0) := r.register3; -- since register3 only has 8 bits when others => v.dat := (others => 'X'); -- Return undefined for all other addresses end case; if wb_rst_i='1' then -- Reset request, put register1 and register2 with zeroes, -- put register 3 with binary 10101010b v.register1 := (others => '0'); v.register2 := (others => '0'); v.register3 := "10101010"; else -- Not reset -- See if we did not acknowledged a cycle, otherwise we need to ignore -- the apparent request, because wishbone signals are still set if r.ack='0' then -- Check if someone is accessing if wb_cyc_i='1' and wb_stb_i='1' then v.ack := '1'; -- Acknowledge the read/write. Actual read data was set above. if wb_we_i='1' then -- Its a write. See for which register based on address case wb_adr_i(3 downto 2) is when "00" => v.register1 := wb_dat_i; -- Set register1 when "01" => v.register2 := wb_dat_i; -- Set register2 when "10" => v.register3 := wb_dat_i(7 downto 0); -- Only lower 8 bits for register3 when others => null; -- Nothing to do for other addresses end case; end if; -- if wb_we_i='1' end if; -- if wb_cyc_i='1' and wb_stb_i='1' end if; -- if ack_i='0' end if; -- if wb_rst_i='1' if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock r <= v; -- Update registers on clock change end if; end process;end rtl;Example 4 -- This example uses asynchronous outputs and record-based registerslibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.numeric_std.all;entity example4 is port ( wb_clk_i: in std_logic; -- Wishbone clock wb_rst_i: in std_logic; -- Wishbone reset (synchronous) wb_dat_o: out std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) wb_dat_i: in std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) wb_adr_i: in std_logic_vector(31 downto 2); -- Wishbone address input (30 bits) wb_we_i: in std_logic; -- Wishbone write enable signal wb_cyc_i: in std_logic; -- Wishbone cycle signal wb_stb_i: in std_logic; -- Wishbone strobe signal wb_ack_o: out std_logic -- Wishbone acknowledge out signal );end entity example4;architecture rtl of example4 is type regstype is record register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits) register2: std_logic_vector(31 downto 0); -- Register 2 (32 bits) register3: std_logic_vector(7 downto 0); -- Register 3 (8 bits) end record; signal r: regstype; -- Main registersbegin -- This is a single process, with mixed asynchronous and synchronous parts process(wb_adr_i,wb_dat_i,wb_clk_i,wb_cyc_i,wb_stb_i,wb_we_i,wb_rst_i,r) variable v: regstype; -- Local variable with register values begin v := r; -- Set v with our saved regs. We use 'v' to write, and 'r' to read -- Always set output asynchronously case wb_adr_i(3 downto 2) is when "00" => wb_dat_o <= r.register1; -- Output register1 when "01" => wb_dat_o <= r.register2; -- Output register2 when "10" => wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero wb_dat_o(7 downto 0) <= r.register3; -- since register3 only has 8 bits when others => wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses end case; if wb_rst_i='1' then -- Reset request, put register1 and register2 with zeroes, -- put register 3 with binary 10101010b v.register1 := (others => '0'); v.register2 := (others => '0'); v.register3 := "10101010"; else -- Not reset if wb_cyc_i='1' and wb_stb_i='1' then wb_ack_o <= '1'; -- Acknowledge the read/write asynchronously. Actual read data was set above. if wb_we_i='1' then -- Its a write. See for which register based on address case wb_adr_i(3 downto 2) is when "00" => v.register1 := wb_dat_i; -- Set register1 when "01" => v.register2 := wb_dat_i; -- Set register2 when "10" => v.register3 := wb_dat_i(7 downto 0); -- Only lower 8 bits for register3 when others => null; -- Nothing to do for other addresses end case; end if; -- if wb_we_i='1' end if; -- if wb_cyc_i='1' and wb_stb_i='1' end if; -- if wb_rst_i='1' if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock r <= v; -- Update registers on clock change end if; end process;end rtl;Alvies_Wishbone_Examples.zip
  25. Maybe someone can answer this for me. When I installed the Windows installer package for Retrocade, I believe it installed TWO instances of the FTDI virtual COM port driver. The FTDI driver was likely installed before for other devices on my computer before installing the package. When I plug in the Papilio board, two COM ports show up, and the location field in the device manager days "on USB Serial Converter B" and "on USB Serial Converter A" > FTDIBUS\COMPORT&VID_0403&PID_6010 Is this supposed to happen? When I tried programming the Papilio with the one COM port nothing happened. Brian