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Found 5 results

  1. IoT Panel - Some pics

    Some pics of my IoT RGB panel board. Took some time to actually take some photos today while assembling one. This is the 9th assembled board. Not final release - I still have to do some modifications (mostly to improve its capabilitites). RGB332 tested OK, perhaps better bitdepth will be possible... working on it. Top view: Xilinx XC2C32 CPLD, in charge of panel control: 3.3 and 1.8 LDO. Caps. Close-up on CPLD. Nice soldering. Thanks Jack to make me go back to Kenston Flux pen. Board top overview, along with stock XC2C32. Bottom view. Passives (mostly caps) and ESP8266 - the heart of the design. And fully assembled board. Some components are optional and not populated. Will be removed in version 1.1. What can it do ? Well, many things.... Let me know if you want to watch some demos. Alvie
  2. HI, I am going to start teaching a course on Xilinx FPGAs. I just found this, apparently wonderful, Papilio DUO board, which, if my understanding is correct, can be used by the Arduino instructors as well. I would like to know: 1) what parts do I need to be able to program the Papilio DUO using Xilinx's software? -> programming cable? 2) is there any recommended additional board that will "do something" using this Xilinx's software?
  3. After finding the software i needed to make use of the design lab, i've encountered some obstacles. It's asking me to fill out company related info.
  4. PapilioOne.ucf# Constraints for the Papilio OneNET CLK32M LOC="P89" | IOSTANDARD=LVTTL | PERIOD=31.25ns; # CLKNET phase_a LOC="P91" | IOSTANDARD=LVTTL; # C0NET phase_b LOC="P92" | IOSTANDARD=LVTTL; # C1NET phase_c LOC="P94" | IOSTANDARD=LVTTL; # C2NET phase_d LOC="P95" | IOSTANDARD=LVTTL; # C3NET sw_dir LOC="P11" | IOSTANDARD=LVTTL; # C15NET sw_enable LOC="P15" | IOSTANDARD=LVTTL; # C13NET sw_speed LOC="P17" | IOSTANDARD=LVTTL; # C11Hello everyone, Can anyone help me what these pins are on Papilio One. I am using Xilinx Spartan 6 FPGA board. Can anyone suggest me what pins on Spartan 6 match with the above UCF file of Spartan 3e. Source:
  5. I'm using Xilinx ISE 14.7 to program a Papilio One 250k. I'm trying to simulate a process that uses a BUFG component, and the output of the component is all 0 -- it doesn't follow the input. Here's a small snippet of code: library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;entity UART is Port ( CLK : in std_logic; -- CLK runs at 32 MHz CLKDIV : in unsigned(15 downto 0); -- divide to bit clock );end UART;architecture Behavioral of UART is signal BITCLK : std_logic := '0'; -- four clocks per bit signal PREBITCLK : std_logic := '0'; component BUFG port( I : in std_logic; O : out std_logic ); end component;begin Bitclk_Bufg: BUFG port map( I => PREBITCLK, O => BITCLK ); Clk_Proc: process(CLK, CLKDIV) variable PREVDIV : unsigned(15 downto 0) := to_unsigned(0, 16); variable CURCNT : unsigned(15 downto 0) := to_unsigned(0, 16); begin if rising_edge(CLK) then if not (PREVDIV = CLKDIV) then CURCNT := to_unsigned(0, 16); PREVDIV := CLKDIV; elsif CURCNT = PREVDIV then CURCNT := to_unsigned(0, 16); PREBITCLK <= not PREBITCLK; else CURCNT := CURCNT + 1; end if; end if; end process;...I see CLK coming in in my simulation, and I see PREBITCLK being generated. However, the BITCLK output is just 0 no matter how long I run the simulation. Why is this? Isn't it supposed to just buffer the clock, and thus repeat the input? How can I make it do that?