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Found 5 results

  1. An LCD driver for the most common lcd controller to be used in fpgas and not only ... Check out the project and code here!!
  2. Me and a partner created a version of the classic Space invaders arcade game in a Zedboard FPGA 100 % in Verilog. Check out the project and code here !!
  3. hello boys, i saw an announce recently about the opensourcing of a 2D/3D commercial GPU of the late nineties: maybe it's good companion for the "soon to come" HDMI wing for Papilio Pro? (or for Pipistrello) bests Andrea PS sadly enough it's in verilog, the "perl" of HDL! :-)
  4. I am coding in Verilog. I am trying to use the MicroJoystick installed on LogicStartMegaWing, the shield with Papilio-One 500k (my FPGA board). I have to do simple tasks like increment or decrement a reg variable on different movements of the joystick. Initially I was running the above code in an alwaya @ (SWITCH) block i.e. the block will be running whenever there is a movement in joystick (on this board joystick shares the pins with five switches). This led to complete loss of control of the cursor on the VGA display (very fast multiple increments or decrements), even on slightest movement of the joystick. Then I ran the same code in an always @ (slowclk) block where 'slowclk' is a 1Hz clock. This led to improvement as there were finite, slower increments or decrements. However, the problem is not completely resolved i.e. on one move of the joystick there are multiple increments to the reg. How can I remove this debounce from the input through the joystick? Need some help on this. I am also putting my code to generate the slowclk and to use the joystick. /////////////// module Slowclock( input clk_25, output reg slowclk ); reg [63:0] i; parameter delay = 12500000; initial begin slowclk = 0; i = 64'd0; end always @ (posedge clk_25) begin if (i < delay) i= i+1; else begin i = 64'd0; slowclk = ~slowclk; end end endmodule ///////////// always @ (slowclk) begin if (SWITCH[0]==0) if (I==0) I <= 3'd5; else I <= I - 1; if (SWITCH1]==0) if (I==5) I <= 3'd0; else I <= I+1; if (SWITCH[3]==0) if (J==5) J <= 3'd0; else J <= J + 1; if (SWITCH[4]==0) if (J==0) J <= 3'd5; else J <= J - 1; end //////////////
  5. I'm trying to build the ./bscan_spi_xc6slx9.bit file from source, to program the flash on my Papilio Pro board. From the git source, the only .v or .vhdl source file for Spartan 6 is: ./xc3sprog/trunk/bscan_spi/bscan_s6_spi_isf_ext.v Is this the one I should use? Then for the User Constraints File, the only relevant one I can find is the generic one, The two files obviously don't match, so I from the .ucf file I removed everything except the FLASH_* lines. And in the .v file, I replaced all the MOSI/MISO lines with the FLASH_SI/SO etc lines, like: module top ( output wire FLASH_SI, //MOSI, output wire FLASH_CS, //CSB, output wire FLASH_CK, //DRCK1, input FLASH_SO //MISO ); (and all other places) The resulting .v & .ucf files do generate a bscan .bit file, but when I use that to program the flash, I get this: ./papilio-prog -f ../Helper_App/Quickstart-Papilio_One_LX9-v1.5.bit -b ~joostje/VHDL/bscan-Papilio/top.bit -v Using built-in device list JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9 Uploading "/home/joostje/VHDL/bscan-Papilio/top.bit". DNA is 0xb9c95021930a5ffe Done. Programming time 547.0 ms Programming External Flash Memory with "../Helper_App/Quickstart-Papilio_One_LX9-v1.5.bit". Uknown Flash Manufacturer (0x00) Error: SPI Status Register [0x00] mismatch (Wrong device or device not ready).. Error occured. USB transactions: Write 178 read 10 retries 8 Using the original bscan_spi_xc6slx9.bit does work: As for the reason why I want to build the source (apart from "I should be able to"), I'm using a modified Papilio board design with a Spartan XC6SLX16 (256 pin BGA), So I need to generate a new bitfile for that XC6SLX16. So, doesn anyone know where the .v or .vhdl source files (preferably with a .ucf file) are that can generate a .bit file for the Spartan 6 (Papilio Pro)? Papilio-Loader source was this morning cloned from here: (I've attached my modified .ucf and .v files, both renamed to .txt as the uploader didn't like my .ucf extention) Thanks, joost BPC3011-Papilio_Pro-general.txt bscan_s6_spi_isf_ext.txt