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If I want to use the FTDI Port B of the FPGA USB port as a serial to USB converter connected to a PC, I understand that I have to use signals BD0 (TXD), BD1 (RXD), BD2 (RTS) and BD3 (CTS) mapped to pins 46, 141, 140, 138 of the FPGA (for full hw handshake). Am I correct ? Is there any interference with the normal Papilio Loader programming ? Regards, José Luis.
Hi! I have a weird problem with my papilio pro board. I am sending large amounts of data over the uart port to an attached computer. Sometimes, the computer reads a nullbyte (0x00), which was not sent by me. I tried ZPUino and Misoc's LM32 on the papilio side and a couple of Java serial libraries as well as pyserial on the computer's side for reading. All with the same problem. Some guys in IRC told me that this might be an hardware related issue an I need to stitch the ground plane together with a bunch of short bridges across signal traces. Is this a well known problem? I am not a hardware expert, so I might need some advice or maybe a picture from a fixed board to exactly know what I need to do. Thank you!