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Found 10 results

  1. Hi all from London (UK.) I'm having fun playing with the new version of Designlab (1.0.7). I have had a Papilio One 500K board with Logicstart Megawing for a while now but haven't had time to do much with it.. I am interested in sound synthesis and would like to know if it is possible to use the YM2149 sound chip component in a schematic with the Logicstart board using the Sigma Delta DAC to send the sound through the on board audio Jack as opposed to using an audio wing like shown in the example. Is this possible? Thanks for any help... Steve.S
  2. Version 1.0


    The LogicStart Shield provides everything needed to get started with VHDL and FPGA development on the Papilio with one convenient and easy to connect circuit board. Note: The LogicStart Shield requires the Papilio DUO board.
  3. File Name: LogicStart Shield Generic UCF File Submitter: Dhia File Submitted: 06 Feb 2015 File Category: Papilio UCF (User Constraint) Files The LogicStart Shield provides everything needed to get started with VHDL and FPGA development on the Papilio with one convenient and easy to connect circuit board. Note: The LogicStart Shield requires the Papilio DUO board. Click here to download this file
  4. Hi all. A quick question.. I have a Logicstart Megawing. Does it leave the Papilio one 500K with any spare pins?? If so, I'd like to Mod the logicstart to accept more I/O on those pins... I want to be able to add MIDI functionality if possible. Thanks again, Steve.
  5. If I program my Papilio Pro + LogicStart to only use the LEDs and switches (leaving everything else unused and omitted from the UCF per other advice here) I notice that all segments of the 7-segment displays glow dimly once it's programmed and active. I wonder: would it be better to set all unused I/O lines to high-impedance to prevent this side-effect - or is that already the default, and I need to choose something else as a default? Or, is this actually a sign of some physical problem? The board looks OK... Since I've been doing more reading than programming and I'm waiting on a new joystick cap I haven't fiddled with the 7-segment displays yet.
  6. (This includes observations and details that may be of use to other new users and those new to the Pro, as well as my own questions to follow.) What I'm using: Papilio Pro v1.3LogicStart MegaWing v1.2Windows 7Xilinx ISE Webpack 14.4 (Xilinx_ISE_DS_Win_14.4_P.49d.3.0 from the Vivado and ISE Design Suites download sub-section)Xilinx Device Pack 2012.4.1 (includes important updates for the WebPack)Papilio Loader-2.4-Setup-noJava (I already have Java)Notes: To the admin: There's a beta 2.0 Loader I stumbled across elsewhere on this site. It appears to be out-of-date.The loader may show an older version on its title bar. I've opened an issue with regard to this but it didn't cause problems for this example.Install the Papilio Loader, the Xilinx WebPack software, and the Xilinx Device Pack. Create the license for the free features of the ISE Design Suite and import that license (which you'll receive via email) to the ISE Design Suite. Open the ISE Design Suite and create a new HDL project with Spartan-6 settings appropriate to the Papilio Pro (Note that "Enable Message Filtering" is optional but useful): (At this point I'm mostly following the Intro to Spartan FPGA book with some important changes.) Add a new source VHDL module. Rather than using the wizard, I pasted in the source for this entity directly from the book (be sure to edit out any cruft if your copy spanned a page-break). Note that the entity name doesn't need to match the module name. Add an Implementation Constraints file (I called mine constraints.ucf). This was a little more tricky, since the pins in the book are for the Papilio One 500K, not the Pro. Retrieve the BPM7003-Papilio-Pro-LogicStart-MegaWing-general.ucf file and use it to find the appropriate pin mappings for the Pro (if you cut-and-paste these from the UCF, be sure to rename them accordingly!) This is what I used: NET SWITCH_0 LOC="P114" | IOSTANDARD=LVTTL; # C0NET SWITCH_1 LOC="P115" | IOSTANDARD=LVTTL; # C1NET LED_0 LOC="P123" | IOSTANDARD=LVTTL; # C8NET LED_1 LOC="P124" | IOSTANDARD=LVTTL; # C9Select the VHD file and you'll see the option in the pane below to "Generate Programming File". Run it. You shouldn't get any warnings or errors for this example. Plug in the Papilio Pro (with the LogicStart wing attached). Ensure the drivers load (it may take a short bit the first time you use it). Start the Loader and select the .bit file you just created in your project area (leave the .bmm and .hex file entries blank). Be sure "SPI Flash" is selected below "Write to". Select "Do Selected Operations" and wait for the programming process to complete successfully (there's troubleshooting info in the book and on the forums here). Try it out! The switches enabled by this module happen to control the LEDs above them. Change things! Swap switch_0 and switch_1 in the architecture section of the design, rebuild and upload again - now the switches control the opposite LEDs. Hopefully you find this quick-start useful! I have some questions which I'll add in the first comment below.
  7. Hi all. I'm enjoying learning VHDL but thought I'd have a look at the Zpuino environment as I have a Papilio 500 and logicstart board. On the page. The link to the bitfile doesn't allow me access. I get permission denied. Is that because I am unworthy or is the bitfile somewhere else? Just thought I'd mention.. cheers, Steve.
  8. Just wondering.... I recieved the Logicstart board a few days ago with thanks. One query though. I had to pay an extra charge of 12.91 GBP (about $20.)for the Post office to release it. :? The rate I paid for at your end was for best way. ($7.) I wasn't expecting to have to pay more at my end. Is this normal?Please let me know. All the best, Steve (mubase)
  9. Hi all. I recieved my LogicStart today so as I have a few hours spare I thought I'd get cracking wth Hamster's PDF of tutorials and info. I've just finished making a 4 bit adder using the swithces and LEDs of the board and would like to know if my code looks right. It seems to work.. From right to left, the switches in 2 groups of 4 seem to add up all the way to 15. The code is here: entity switches_leds is Port ( switches : in STD_LOGIC_VECTOR(7 downto 0);LEDs : out STD_LOGIC_VECTOR(7 downto 0));end switches_leds;architecture Behavioral of switches_leds issignal x : STD_LOGIC_VECTOR (3 downto 0);signal y : STD_LOGIC_VECTOR (3 downto 0);signal carry : STD_LOGIC_VECTOR (3 downto 0);signal result : STD_LOGIC_VECTOR (4 downto 0);beginLEDs <= "000" & result;x <= switches (3 downto 0);y <= switches ( 7 downto 4 );result(0) <= x(0) XOR y(0);carry(0) <= x(0) AND y(0);result(1) <= x(1) XOR y(1) XOR carry(0);carry(1) <= (x(1) AND y(1)) OR (carry(0) AND x(1)) OR (carry(0) AND y(1));result(2) <= x(2) XOR y(2) XOR carry(1);carry(2) <= (x(2) AND y(2)) OR (carry(1) AND x(2)) OR (carry(1) AND y(2));result(3) <= x(3) XOR y(3) XOR carry(2);carry(3) <= (x(3) AND y(3)) OR (carry(2) AND x(3)) OR (carry(2) AND y(3));--result(4) <= x(4) XOR y(4) XOR carry(3);--carry(4) <= x(4) AND y(4) OR (carry(3) AND x(4)) OR (carry(3) AND y(4));end Behavioral; I have some boolean experience having gone to college to do an access course in Audio electronics/music technology and being thrown in the deep end of boolean logic. :s At the time all of us in the class were wondering where it all fitted in with Audio systems electronics but I am glad of it now. If someone could verify this for me I'd be much appreciative. All the best, Steve.
  10. Version 1.0


    This bit file loads the ZPUino soft processor with 160x120x8 VGA Output to the Papilio One 500K board and connects the VGA output to the LogicStart MegaWing. This ZPUino variant is derived from the "Hyperion" (God of Light) variant. VGA library reference is here. Source code for the LogicStart variant. Get Started with the ZPUino.