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Found 6 results

  1. Hello, I'm using a papilio one 500k and a logic-start mega wing. I'm looking at the generic UCF file: # UCF file for the Papilio One 500K board# Generated by pin_converter, written by Kevin Lindsey# Main board wing pin [] to FPGA pin Pxx map# -------C------- -------B------- -------A-------# [GND] [C00] P91 [GND] [B00] P85 P86 [A15]# [2V5] [C01] P92 [2V5] [B01] P83 P84 [A14]# [3V3] [C02] P94 [3V3] [B02] P78 P79 [A13]# [5V0] [C03] P95 [5V0] [B03] P71 P70 [A12]# [C04] P98 [B04] P68 P67 [A11] [5V0]# [C05] P2 [B05] P66 P65 [A10] [3V3]# [C06] P3 [B06] P63 P62 [A09] [2V5]# [C07] P4 [B07] P61 P60 [A08] [GND]# [GND] [C08] P5 [GND] [B08] P58 P57 [A07]# [2V5] [C09] P9 [2V5] [B09] P54 P53 [A06]# [3V3] [C10] P10 [3V3] [B10] P41 P40 [A05]# [5V0] [C11] P11 [5V0] [B11] P36 P35 [A04]# [C12] P12 [B12] P34 P33 [A03] [5V0]# [C13] P15 [B13] P32 P26 [A02] [3V3]# [C14] P16 [B14] P25 P23 [A01] [2V5]# [C15] P17 [B15] P22 P18 [A00] [GND]## Prohibit the automatic placement of pins that are connected to VCC or GND for configuration.CONFIG PROHIBIT=P99;CONFIG PROHIBIT=P43;CONFIG PROHIBIT=P42;CONFIG PROHIBIT=P39;CONFIG PROHIBIT=P49;CONFIG PROHIBIT=P48;CONFIG PROHIBIT=P47;CONFIG PART=XC3S500E-VQ100-4;NET CLK LOC="P89" | IOSTANDARD=LVTTL | PERIOD=31.25ns; # CLKNET RX LOC="P90" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # RXNET TX LOC="P88" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # TXNET Seg7_AN(3) LOC="P18" | IOSTANDARD=LVTTL; # A0NET Seg7_DP LOC="P23" | IOSTANDARD=LVTTL; # A1NET Seg7_AN(2) LOC="P26" | IOSTANDARD=LVTTL; # A2NET Seg7_E LOC="P33" | IOSTANDARD=LVTTL; # A3NET Seg7_F LOC="P35" | IOSTANDARD=LVTTL; # A4NET Seg7_C LOC="P40" | IOSTANDARD=LVTTL; # A5NET Seg7_D LOC="P53" | IOSTANDARD=LVTTL; # A6NET Seg7_A LOC="P57" | IOSTANDARD=LVTTL; # A7NET Seg7_AN(1) LOC="P60" | IOSTANDARD=LVTTL; # A8NET Seg7_G LOC="P62" | IOSTANDARD=LVTTL; # A9NET Seg7_B LOC="P65" | IOSTANDARD=LVTTL; # A10NET Seg7_AN(0) LOC="P67" | IOSTANDARD=LVTTL; # A11NET SPI_CS LOC="P70" | IOSTANDARD=LVTTL; # A12NET SPI_MISO LOC="P79" | IOSTANDARD=LVTTL; # A13NET SPI_MOSI LOC="P84" | IOSTANDARD=LVTTL; # A14NET SPI_SCLK LOC="P86" | IOSTANDARD=LVTTL; # A15NET VGA_VSYNC LOC="P85" | IOSTANDARD=LVTTL; # B0NET VGA_HSYNC LOC="P83" | IOSTANDARD=LVTTL; # B1NET VGA_BLUE(0) LOC="P78" | IOSTANDARD=LVTTL; # B2NET VGA_BLUE(1) LOC="P71" | IOSTANDARD=LVTTL; # B3NET VGA_GREEN(0) LOC="P68" | IOSTANDARD=LVTTL; # B4NET VGA_GREEN(1) LOC="P66" | IOSTANDARD=LVTTL; # B5NET VGA_GREEN(2) LOC="P63" | IOSTANDARD=LVTTL; # B6NET VGA_RED(0) LOC="P61" | IOSTANDARD=LVTTL; # B7NET VGA_RED(1) LOC="P58" | IOSTANDARD=LVTTL; # B8NET VGA_RED(2) LOC="P54" | IOSTANDARD=LVTTL; # B9NET AUDIO LOC="P41" | IOSTANDARD=LVTTL; # B10NET JOY_RIGHT LOC="P36" | IOSTANDARD=LVTTL; # B11NET JOY_LEFT LOC="P34" | IOSTANDARD=LVTTL; # B12NET JOY_DOWN LOC="P32" | IOSTANDARD=LVTTL; # B13NET JOY_UP LOC="P25" | IOSTANDARD=LVTTL; # B14NET JOY_SELECT LOC="P22" | IOSTANDARD=LVTTL; # B15NET SWITCH(0) LOC="P91" | IOSTANDARD=LVTTL; # C0NET SWITCH(1) LOC="P92" | IOSTANDARD=LVTTL; # C1NET SWITCH(2) LOC="P94" | IOSTANDARD=LVTTL; # C2NET SWITCH(3) LOC="P95" | IOSTANDARD=LVTTL; # C3NET SWITCH(4) LOC="P98" | IOSTANDARD=LVTTL; # C4NET SWITCH(5) LOC="P2" | IOSTANDARD=LVTTL; # C5NET SWITCH(6) LOC="P3" | IOSTANDARD=LVTTL; # C6NET SWITCH(7) LOC="P4" | IOSTANDARD=LVTTL; # C7NET LED(0) LOC="P5" | IOSTANDARD=LVTTL; # C8NET LED(1) LOC="P9" | IOSTANDARD=LVTTL; # C9NET LED(2) LOC="P10" | IOSTANDARD=LVTTL; # C10NET LED(3) LOC="P11" | IOSTANDARD=LVTTL; # C11NET LED(4) LOC="P12" | IOSTANDARD=LVTTL; # C12NET LED(5) LOC="P15" | IOSTANDARD=LVTTL; # C13NET LED(6) LOC="P16" | IOSTANDARD=LVTTL; # C14NET LED(7) LOC="P17" | IOSTANDARD=LVTTL; # C15NET JTAG_TMS LOC="P75" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TMSNET JTAG_TCK LOC="P77" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TCKNET JTAG_TDI LOC="P100" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDINET JTAG_TDO LOC="P76" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDONET FLASH_CS LOC="P24" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CSNET FLASH_CK LOC="P50" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CKNET FLASH_SI LOC="P27" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_SINET FLASH_SO LOC="P44" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # FLASH_SOWhich one of these nets is the MISO, MOSI, CS, and CLK for the ADC?
  2. Note: this is crossposted from stackexchage , I hope this doesn't go against the forum netiquette (feel free to erase it otherwise) Background Similarly to what Jeri Ellsworth did in her C64 Bass Guitar hack I am working on an audio-to-midi converter for my bass guitar. I am also planning to use piezo discs as sensors placed under each string, connected to a Papilio One, using the ADC of the Logic Start MegaWing (an ADC128S102). The ADC reference voltage is hardwired to 3.3. volts. My problem is that my analog electronics knowledge is pretty bad and I don't have any practical experience (I have given a try to the relevant chapter of the The Data Conversion Handbook but it's a bit too advanced for me). Question What circuit should I use to drive the ADC? The circuit should Implement an anti-aliasing filter. The frequency ranges (excluding harmonics) typically found in each string of a 4-string bass are: E string: E1 (41.20 Hz) to E3 (164.81 Hz) A string: A1 (55.00 Hz) to A3 (220.00 Hz) D string: D2 (73.42 Hz) to D4 (293.66 Hz) G string: G2 (98.00 Hz) to G4 (392.00 Hz) Ensure that the input signal voltage matches the expected range of the ADC (0V to 3.3V as I understand it).I would appreciate as much practical information as possible (e.g. specific circuits and specific parts to use) since, as I have said, I am pretty unexperienced on this. Pointers to books/articles suitable for a newbie like me would also be appreciated.
  3. Hi, I saw this video from Jeri Ellsworth, in which she creates a bass guitar synth using a Papilio One to do the real-time string frequency analysis. I would like to know how she does the ADC conversion. I am new to FPGA's but AFAIK the Spartan 3E doesn't accept analog inputs. Am I right? Do you think she is using an ADC wing? In the video, it looks like look like she is plugin in the 4 analog inputs directly to the FPGA though, see
  4. I recently purchased this bundle from gadget factory. I am new to FPGAs but I have coded with Arduinos before. I understand that FPGAs are alot more useful since then can do operations in parallel as opposed to sequences (arduinos; which is why i purchased it). How can I use the ADC of the megawing? Ideally I have two analog inputs, which sample at the same frequency (250hz). I would then like to output this on a graph (maybe serial port on the computer? or a TFT screen?) Can some one show me to the right direction? Thanks.
  5. Hello, I was wondering if anybody has a means of attaching a LCD screen onto the papilio where we could graph inputs from the adc? It was a pretty simple process to do on arduino. Thanks
  6. So, I was thinking about getting a Papilio one but I have some questions: Is it possible to realize an ADC using sigma delta? Something like this: http://www.hitequest.../adc_dsigma.jpg What is the stability of the DAC using sigma delta? Can I use it to control analogue synthesizers, that is, is it stable or jittery? In a modular, oscillators are controlled using "control-voltage" where 1volt = one octave so that's 0.083333... volts per semitone. That means a 0.001 jitter will be audible instability. So I will probably need an external dac or? I will need to amplify the output to cover something like a +/-5 volts range (10 octaves). I hate smd soldering, any other options for high-res dacs?