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Found 6 results

  1. hi, i'm using designlab 1.0.8 with ise 14.7 on ubuntu 17.04 amd64, targeting a papilio pro/spartan 6 with the zpuino soft processor. i've got a working proof-of-concept design which combines a few bits and pieces, namely the whirlyfly (whirlygig) random number generator (https://github.com/zdavkeos/whirlyfly), a couple wishbone uart's (COMM_zpuino_wb_UART.vhd), and a wishbone watchdog peripheral written in verilog that i've been trying to integrate (https://github.com/freecores/watchdog/tree/master/rtl/verilog). the rng and uart components appear to be working fine, giving me up to 280KB/s or so of random data when polling both wishbone uart's sequentially at 3mbit/s. i'm then using the reference blake2s hash implementation (https://github.com/mjosaarinen/blake2_mjosref) to further "whiten" the output of the rng's. this slows down the output to about 30KB/s which is fine considering it's a complex operation. that's not the issue. anyhow, the wishbone peripherals included in designlab, as well as the schematic representation of the zpuino 2.0 soft processor bundle the input and output wires into the wishbone_in/wishbone_out connections, which i assume is for simplicity when placing components using the schematic editor in ise. the watchdog.v implementation linked previously is designed with all of the wishbone wires broken out like: module watchdog(wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_int_o); i've been trying unsuccessfully now for a while to modify the watchdog.v to present the same interface, so i can easily attach it to the zpuino using the schematic editor gui (i.e. Papilio_Pro.sch) in ise. without knowing how to modify the schematic symbol after generating it, i just took the one from the wishbone uart included in designlab, replaced the relevant variables and removed the tx/rx, and overwrote the existing watchdog.sym in the project directory. that seemed to work fine and let me drag & drop the watchdog onto an open wishbone port on the zpuino. the issue i'm having is that i can't seem to get the pre-synthesis rtl schematic viewer in planahead to "alias" the slices of wishbone_in/wishbone_out to the friendly-named wires representative of their function within the wishbone bus (e.g. wire [31:0] wb_dat_i; assign wb_dat_i [31:0] = wishbone_in [59:28];). the design does synthesize fine, but i haven't bothered trying to write C code for the zpuino to interface/write with the watchdog peripheral because of the apparent brokenness being shown in planahead. here's a simplification of what i've been doing unsuccessfully to create the "friendly" aliases of wishbone_in/wishbone_out: // original, simplified module watchdog(wb_clk_i, wb_rst_i, wb_dat_i, ...); parameter Tp = 1; input wb_clk_i; input wb_rst_i; input [`WDT_WIDTH - 1:0] wb_dat_i; ... // new, simplified module watchdog(wishbone_in, wishbone_out); parameter Tp = 1; input [100:0] wishbone_in; output [100:0] wishbone_out; wire wb_clk_i = wishbone_in [61]; wire wb_rst_i = wishbone_in [60]; wire [31:0] wb_dat_i; assign wb_dat_i [31:0] = wishbone_in [59:28]; ... // mutual code between original & new ... always @(posedge wb_rst_i or posedge wb_clk_i) if (wb_rst_i) begin stb <= #Tp 1'b0; we <= #Tp 1'b0; dat_ir <= #Tp `WDT_WIDTH'h0; end else begin stb <= #Tp wb_stb_i && wb_cyc_i; we <= #Tp wb_we_i; dat_ir <= #Tp wb_dat_i; end ... attached are abridged screenshots of what planahead shows for the unmodified verilog code straight from the aforementioned github repo (top image), and the seemingly broken output from my modified version where i try to bundle up the wires into wishbone_in/wishbone_out. the dat_ir is where wb_dat_i is showing a single wire instead of [31:0]. also attached is the work-in-progress modified watchdog.v. please keep in mind that these are the first lines of vhdl/verilog i've ever written so my knowledge of syntax/terminology is very limited. thanks! watchdog.v
  2. Dear Altruists, I'm new to Papilio Pro FPGA. I designed my circuit with VHDL and also synthesized it, and it is ready to be loaded in the papilio pro fpga. My circuits interface has an input of 64 bits and output of 1 bit. I need only to send this 64 bit data from my pc to FPGA and receive the output of 1 bit ( please check the uploaded circuit interface). I already watched most of the learning videos. I have already contacted Mr. Alvie and thanks to him he reply with an answer, but it was a little difficult for me to understand as I am new to FPGA. His answer was that I should connect my circuits to one of wishbone ZPUino slots, and use ZPUino to interface with the USB/serial using software moving data to and form my circuits. However, the things that I don't understand are that: 1. Should i connect my circuits to wishbone bridge and then connect my circuits to the wishbone slots as you did here ( http://gadgetfactory.net/learn/2015/05/14/designlab-libraries-make-a-wishbone-library-2/). If the answer yes, should I connect the the both input and output to the wishbone bridge. If answer no, then should I interface my circuits directly to the ZPUino wishbone slots. 2. If I connect my circuits to ZPUino wishbone slots. The input 64 bits and the output 1 bit should be connected to what to the slots or Paplilio Pro Pins. 3. Mr. Jack illustrate in the learning site videos that ZPUino should be loaded to the SPI not to the FPGA Spartan6. So, If I am going to interface my design to ZPUino how can I load the circuits to the FPGA. 4. If I am going to make an interface of the UART I think I just need to follow as same as Mr. Jack did in this video( http://gadgetfactory.net/learn/2013/11/15/papilio-schematic-library-10-serial-ports/ ) Please forgive my shortcomings. I am new to these things. Any help will be highly appreciated. Thanks
  3. Hi, I wonder how the access to the on-board RAM can be implemented and organized. So far I know that a ZPUino uses the on-board RAM to store programs and data. If I understand it correctly, the ZPUino implementation uses the sram_ctl8.vhd source to access the RAM chip via a Wishbone bus interface. I want to use the Papilio DUO to simulate an expansion board for an old 6502-based computer (Ohio Scientific Challenger 1P). On the one hand I want to use a part of the Papilio DUO RAM chip as a memory expansion for the 6502 board. On the other hand a floppy controller with attached floppy disks shall be simulated with storage on an SD card. So for the RAM expansion alone I only need to translate the 6502 bus to something that can communicate with the Papilio DUO's RAM chip. I either could create a Wishbone bus wrapper around the 6502 bus, and use the sram_ctl8.vhd as-is, or I could directly build a bridge from the 6502 bus to the RAM chip based on the internals of the sram_ctl8.vhd source. But when the floppy controller comes into the picture it gets more complicated. I need to simulate some of the chips for the floppy controller (6850 ACIA and 6820 PIA) and map them into the address space of the 6502. For access to an SD card I will either need to use a ZPUino or the real ATmega32U4 processor. With a ZPuino I would need to divide the RAM between the memory expansion and the ZPUino. So lots of questions arise: How can I divide the RAM between the ZPUino and other parts of my design? Could that be managed with compile and link time options when building the sketch for the ZPUino, or would I need to build something in VHDL? Is it even possible at all to influence the ZPUino's use of the RAM chip without modifying its implementation? Would it be better to use the ATmega32U4 for implementing the access to the SD card? I'm obviously at the very beginner level regarding designing and implementing such a project, so I would be very grateful about any tips and experiences in this area. Thanks Stephan
  4. Hello, Im having a problem with the wishbone interface on the ZPUino soft processor. I am trying to output a signal to a design I have made, in this instance its outputting a reset signal but the same problem occurs on all the other outputs too. The signal and corresponding pin I have the oscilloscope connected to is highlighted in red in fig 1. This goes to a custom block that builds individual signals into a bus that is outputted using the Papilio block set provided, this can be seen in fig 2. Im using the standard ZPUino programing IDE, when I program it to output 0xff to wishbone Register 2 the output pin on the FPGA becomes high, this is shown in figure 3. This is exactly what you would expect to happen. Again in fig 4 the when Register 2 is set to be 0x00 then the output on the pin connected to the oscilloscope is set to logic 0, as expected. However in figure 5 Wishbone register 2 is set to be 0x00 for 100ms then set to 0xff for 200ms, this should produce a waveform that shows a signal that is high twice as long as low. Though this is the comes out as the opposite, it seems that the signal is being inverted. I can’t for the life of me work out why this is. Similarly in fig 6 I set it to be the opposite 0xff for 200ms and 0x00 for 100ms and it does the same, inverting the signals again. I have checked for sources of error in other places, the oscilloscope is working fine Ive tried connecting the Wishbone output directly to a pin to see if the Papilio output block was the cause this had no effect, I’ve double checked my Wishbone interface code its fine no reason to invert the output. This also happens when the delay is increased to 20secconds and 10secconds to see if it was a timing issue and needed a steeling time, keeps inverting the signals still. The weird thing is that it works fine when the is no periodic signal applied and its just a DC output, if it was an inverter causing the problem that’s fine all I need to do is change my code around a bit but this is not that simple and I couldn’t work with an unpredictable output. Does anyone have any suggestion as to what the problem is? Many thanks Joe
  5. Hi All, I've been getting back into some Papilio development again lately and have been very happy to see all the improvements to the SoC ecosystem. I've been able to reproduce the pwn tutorial (very helpful!) and now want to add a toy 'adder' (add two registers and store the result in a third) component. I'm struggling to understand the behavior of async vs sync from the perspective of software running on zpuino. With an async result do you poll for a ready bit, vs having the cpu block on sync? Are there software examples of the two, or best practices to follow? The default template is async, and the vhdl code makes sense, I'm just wondering… for the adder component described above, should I be using sync? (I've seen the examples of that in another thread). Thanks in advance, -Greg
  6. A while back I asked Alvie if he had any easy to understand templates for a wishbone peripheral that could be plugged into the ZPUino. He quickly threw together four examples and sent them to me but I never got a chance to do anything with them. I was just looking them over today when I realized I should probably post these to the forums so everyone can enjoy them! So here goes: Example 1 -- This example uses asynchronous outputs.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.numeric_std.all;entity example1 is port ( wb_clk_i: in std_logic; -- Wishbone clock wb_rst_i: in std_logic; -- Wishbone reset (synchronous) wb_dat_o: out std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) wb_dat_i: in std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) wb_adr_i: in std_logic_vector(31 downto 2); -- Wishbone address input (30 bits) wb_we_i: in std_logic; -- Wishbone write enable signal wb_cyc_i: in std_logic; -- Wishbone cycle signal wb_stb_i: in std_logic; -- Wishbone strobe signal wb_ack_o: out std_logic -- Wishbone acknowledge out signal );end entity example1;architecture rtl of example1 is signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits) signal register2: std_logic_vector(31 downto 0); -- Register 2 (32 bits) signal register3: std_logic_vector(7 downto 0); -- Register 3 (8 bits)begin -- Asynchronous acknowledge wb_ack_o <= '1' when wb_cyc_i='1' and wb_stb_i='1' else '0'; -- Multiplex the data output (asynchronous) process(register1,register2,register3, wb_adr_i) begin -- Multiplex the read depending on the address. Use only the 2 lowest bits of addr case wb_adr_i(3 downto 2) is when "00" => wb_dat_o <= register1; -- Output register1 when "01" => wb_dat_o <= register2; -- Output register2 when "10" => wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero wb_dat_o(7 downto 0) <= register3; -- since register3 only has 8 bits when others => wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses end case; end process; process(wb_clk_i) begin if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock if wb_rst_i='1' then -- Reset request, put register1 and register2 with zeroes, -- put register 3 with binary 10101010b register1 <= (others => '0'); register2 <= (others => '0'); register3 <= "10101010"; else -- Not reset -- Check if someone is writing if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then -- Yes, its a write. See for which register based on address case wb_adr_i(3 downto 2) is when "00" => register1 <= wb_dat_i; -- Set register1 when "01" => register2 <= wb_dat_i; -- Set register2 when "10" => register3 <= wb_dat_i(7 downto 0); -- Only lower 8 bits for register3 when others => null; -- Nothing to do for other addresses end case; end if; end if; end if; end process;end rtl;Example 2 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.numeric_std.all;entity example2 is port ( wb_clk_i: in std_logic; -- Wishbone clock wb_rst_i: in std_logic; -- Wishbone reset (synchronous) wb_dat_o: out std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) wb_dat_i: in std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) wb_adr_i: in std_logic_vector(31 downto 2); -- Wishbone address input (30 bits) wb_we_i: in std_logic; -- Wishbone write enable signal wb_cyc_i: in std_logic; -- Wishbone cycle signal wb_stb_i: in std_logic; -- Wishbone strobe signal wb_ack_o: out std_logic -- Wishbone acknowledge out signal );end entity example2;architecture rtl of example2 is signal register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits) signal register2: std_logic_vector(31 downto 0); -- Register 2 (32 bits) signal register3: std_logic_vector(7 downto 0); -- Register 3 (8 bits) signal ack_i: std_logic; -- Internal ACK signal (flip flop)begin -- This example uses fully synchronous outputs. wb_ack_o <= ack_i; -- Tie ACK output to our flip flop process(wb_clk_i) begin if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock -- Always set output data on rising edge, even if reset is set. case wb_adr_i(3 downto 2) is when "00" => wb_dat_o <= register1; -- Output register1 when "01" => wb_dat_o <= register2; -- Output register2 when "10" => wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero wb_dat_o(7 downto 0) <= register3; -- since register3 only has 8 bits when others => wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses end case; ack_i <= '0'; -- Reset ACK value by default if wb_rst_i='1' then -- Reset request, put register1 and register2 with zeroes, -- put register 3 with binary 10101010b register1 <= (others => '0'); register2 <= (others => '0'); register3 <= "10101010"; else -- Not reset -- See if we did not acknowledged a cycle, otherwise we need to ignore -- the apparent request, because wishbone signals are still set if ack_i='0' then -- Check if someone is accessing if wb_cyc_i='1' and wb_stb_i='1' then ack_i<='1'; -- Acknowledge the read/write. Actual read data was set above. if wb_we_i='1' then -- Its a write. See for which register based on address case wb_adr_i(3 downto 2) is when "00" => register1 <= wb_dat_i; -- Set register1 when "01" => register2 <= wb_dat_i; -- Set register2 when "10" => register3 <= wb_dat_i(7 downto 0); -- Only lower 8 bits for register3 when others => null; -- Nothing to do for other addresses end case; end if; -- if wb_we_i='1' end if; -- if wb_cyc_i='1' and wb_stb_i='1' end if; -- if ack_i='0' end if; -- if wb_rst_i='1' end if; -- if rising_edge(wb_clk_i) end process;end rtl;Example 3 -- This example uses fully synchronous outputs and record-based registerslibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.numeric_std.all;entity example3 is port ( wb_clk_i: in std_logic; -- Wishbone clock wb_rst_i: in std_logic; -- Wishbone reset (synchronous) wb_dat_o: out std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) wb_dat_i: in std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) wb_adr_i: in std_logic_vector(31 downto 2); -- Wishbone address input (30 bits) wb_we_i: in std_logic; -- Wishbone write enable signal wb_cyc_i: in std_logic; -- Wishbone cycle signal wb_stb_i: in std_logic; -- Wishbone strobe signal wb_ack_o: out std_logic -- Wishbone acknowledge out signal );end entity example3;architecture rtl of example3 is type regstype is record register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits) register2: std_logic_vector(31 downto 0); -- Register 2 (32 bits) register3: std_logic_vector(7 downto 0); -- Register 3 (8 bits) ack: std_logic; -- Ack signal to output (register/ff) dat: std_logic_vector(31 downto 0); -- Data out register/ff end record; signal r: regstype; -- Main registersbegin wb_ack_o <= r.ack; -- Tie ACK output to our flip flop wb_dat_o <= r.dat; -- And data out also -- This is a single process, with mixed asynchronous and synchronous parts process(wb_adr_i,wb_dat_i,wb_clk_i,wb_cyc_i,wb_stb_i,wb_we_i,wb_rst_i,r) variable v: regstype; -- Local variable with register values begin v := r; -- Set v with our saved regs. We use 'v' to write, and 'r' to read -- Always set output data on rising edge, even if reset is set. case wb_adr_i(3 downto 2) is when "00" => v.dat := r.register1; -- Output register1 when "01" => v.dat := r.register2; -- Output register2 when "10" => v.dat(31 downto 0) := (others => '0'); -- We put all upper 24 bits to zero v.dat(7 downto 0) := r.register3; -- since register3 only has 8 bits when others => v.dat := (others => 'X'); -- Return undefined for all other addresses end case; if wb_rst_i='1' then -- Reset request, put register1 and register2 with zeroes, -- put register 3 with binary 10101010b v.register1 := (others => '0'); v.register2 := (others => '0'); v.register3 := "10101010"; else -- Not reset -- See if we did not acknowledged a cycle, otherwise we need to ignore -- the apparent request, because wishbone signals are still set if r.ack='0' then -- Check if someone is accessing if wb_cyc_i='1' and wb_stb_i='1' then v.ack := '1'; -- Acknowledge the read/write. Actual read data was set above. if wb_we_i='1' then -- Its a write. See for which register based on address case wb_adr_i(3 downto 2) is when "00" => v.register1 := wb_dat_i; -- Set register1 when "01" => v.register2 := wb_dat_i; -- Set register2 when "10" => v.register3 := wb_dat_i(7 downto 0); -- Only lower 8 bits for register3 when others => null; -- Nothing to do for other addresses end case; end if; -- if wb_we_i='1' end if; -- if wb_cyc_i='1' and wb_stb_i='1' end if; -- if ack_i='0' end if; -- if wb_rst_i='1' if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock r <= v; -- Update registers on clock change end if; end process;end rtl;Example 4 -- This example uses asynchronous outputs and record-based registerslibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.numeric_std.all;entity example4 is port ( wb_clk_i: in std_logic; -- Wishbone clock wb_rst_i: in std_logic; -- Wishbone reset (synchronous) wb_dat_o: out std_logic_vector(31 downto 0); -- Wishbone data output (32 bits) wb_dat_i: in std_logic_vector(31 downto 0); -- Wishbone data input (32 bits) wb_adr_i: in std_logic_vector(31 downto 2); -- Wishbone address input (30 bits) wb_we_i: in std_logic; -- Wishbone write enable signal wb_cyc_i: in std_logic; -- Wishbone cycle signal wb_stb_i: in std_logic; -- Wishbone strobe signal wb_ack_o: out std_logic -- Wishbone acknowledge out signal );end entity example4;architecture rtl of example4 is type regstype is record register1: std_logic_vector(31 downto 0); -- Register 1 (32 bits) register2: std_logic_vector(31 downto 0); -- Register 2 (32 bits) register3: std_logic_vector(7 downto 0); -- Register 3 (8 bits) end record; signal r: regstype; -- Main registersbegin -- This is a single process, with mixed asynchronous and synchronous parts process(wb_adr_i,wb_dat_i,wb_clk_i,wb_cyc_i,wb_stb_i,wb_we_i,wb_rst_i,r) variable v: regstype; -- Local variable with register values begin v := r; -- Set v with our saved regs. We use 'v' to write, and 'r' to read -- Always set output asynchronously case wb_adr_i(3 downto 2) is when "00" => wb_dat_o <= r.register1; -- Output register1 when "01" => wb_dat_o <= r.register2; -- Output register2 when "10" => wb_dat_o(31 downto 0) <= (others => '0'); -- We put all upper 24 bits to zero wb_dat_o(7 downto 0) <= r.register3; -- since register3 only has 8 bits when others => wb_dat_o <= (others => 'X'); -- Return undefined for all other addresses end case; if wb_rst_i='1' then -- Reset request, put register1 and register2 with zeroes, -- put register 3 with binary 10101010b v.register1 := (others => '0'); v.register2 := (others => '0'); v.register3 := "10101010"; else -- Not reset if wb_cyc_i='1' and wb_stb_i='1' then wb_ack_o <= '1'; -- Acknowledge the read/write asynchronously. Actual read data was set above. if wb_we_i='1' then -- Its a write. See for which register based on address case wb_adr_i(3 downto 2) is when "00" => v.register1 := wb_dat_i; -- Set register1 when "01" => v.register2 := wb_dat_i; -- Set register2 when "10" => v.register3 := wb_dat_i(7 downto 0); -- Only lower 8 bits for register3 when others => null; -- Nothing to do for other addresses end case; end if; -- if wb_we_i='1' end if; -- if wb_cyc_i='1' and wb_stb_i='1' end if; -- if wb_rst_i='1' if rising_edge(wb_clk_i) then -- Synchronous to the rising edge of the clock r <= v; -- Update registers on clock change end if; end process;end rtl;Alvies_Wishbone_Examples.zip