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Found 11 results

  1. hello, i am an engineering student and as my final project i am required to make a working project with VHDL programming language. i was told to use Papilio DUO programmable board to make my project, but i dont know how to program it since i was working with MOJO 3V before it stopped working. my question is can i program Papilio DUO with simple VHDL programming language and not drawing the circuits?
  2. I want to learn VHDL, and I am searching for a cheap and flexible board to be my learning partner. Currently I have only done pretty simple VHDL stuff using CPLDs and Xilinx ISE tools, and I want to make the jump to more complex stuff. Papilio boards look nice, but as they look targeted to "non HDL friendly people", I'm wondering if I will have problems using Xilinx tools instead of Papilio tools. I was thinking about buying a Papilio Pro board, with an Arcade Mega Wing. I suppose it will fit the Papilio Pro without problems, but I'm not 100% sure, maybe it's only for Papilio One? Thanks for help!
  3. Hi, Do you guys know of a reliable open source method to perform hardware verification on the AVR8 Soft core? I know using the VHDL code for the AVR8 with Xilinx ISE Web pack software helps us to debug code written in the Arduino IDE, but is there a way to maybe integrate both and automate it? Thanks,
  4. Although current ZPUino timers implement a very complex and capable PWM system, we are struggling a bit to integrate PWM and Timer support at same time in ZPUino code. It's rather hard to mix both in a sensible way, because timers can have been claimed for other modules, and PWM may not always be able to map the correct pin, or map the correct timer, and fixing this in software will end up with a bit mess of code and bugs. So, after a quick chat with Jack a few days ago, we concluded that it would be better to have a separate PWM module from now on. But we are not entirely sure of what you users may need/want from such a module. I have spent last couple of days thinking about this, and I have come to a preliminary design which I'd like you to comment on. This design is based on my previous experience with a very PWM-capable generator - the Texas Instruments TMS320F series. I have borrowed some ideas from them, and my plan is roughly to have something like this (I have already implemented most of it, actually): -- Overall Module view - 16-bit counter, 8-bit prescaler. Up to 4 PWM compare/output blocks. - Each output block has 2 outputs. - Sync-in/Sync-out support for cascading more modules (if for example different timebases are needed) and to keep them perfectly synchronized. - Interrupt support. - Clocking block - 8-bit prescaler. Can divide the main clock by anything from 1 to 255. - Only meant to be programmed once. Subsequent programming may lead to glitches. - Per-module clock enable/disable. - Counter block - Three modes: count-up, count-down, and count-up-down - 16-bit period, with shadow register configurable. Phase counter for sync-in. - Compare block (up to 4 blocks per module) - 2 comparators (A and with 16-bit comparator. - Shadowing support - Output module (up to 4 blocks per module) - 2 outputs. - Each output configurable to both A/B comparators, zero or overflow. Can either set, clear, toggle or no-op on output pin. Comments ? Alvie
  5. I had a copy of Lady Bug written by Arnim Laeuger, that I downloaded from fpgaarcade a long long time ago and forgot all about it. I recently came across it and I spent a little time getting it going for the Papilio. Unfortunately it won't fit on a Papilio One, it uses about 28 BRAMs and the Papilio One doesn't have any external memory and not enough internal memory. Good news is, it will fit entirely into a Papilio Pro or any Spartan 6 FPGA without needing any external RAM or ROM. Getting this ported to the Papilio was just a matter of writing a top level module to connect the ladybug machine to the various ROMs and input controls. This is the first time I've finally used a PS2 keyboard controller from here which appears to have a well written bidirectional PS2 controller. Bidirectional means that when you hit for example the caps lock key, the PS2 controller detects that and sends data back to the keyboard to turn on the caps lock LED. The key mapping I chose can be easily changed if you look in the source code and have a handy PS2 key code reference. As is, the game should be playable with the arrow keys. A small issue, if you have your monitor tilted one way to get other games like Pacman showing correctly, then Ladybug will appear upside down. If you can tilt the monitor the other way, you're all set, if however you can't and just reverse the state of the flip_screen_g variable, the screen will appear at first glance to be correctly flipped but unfortunately only the background is flipped, the sprites and key mapping are not, so, for example, Ladybug will appear to move the wrong way, won't line up with the corridors, eating the dots on one side of the screen causes the dots on the opposite side to disappear, etc. Currently three games are supported: Ladybug, Dorodon (a Ladybug like clone) and Cosmic Avenger (a Defender like clone). I haven't searched what other ROMs the original hardware supported, if any. The source code is available here. To make it all work, download the source then download and place the game ROMs into the appropriate ROMs folder. See the readme file in each folder for a list of the files and checksums you should be looking for, If you're on Windows, run the make_roms batch file in the relevant game rom folder. Game ROMs will be converted to vhdl files in the build directory. If you're on linux, there appears to be a makefile based system for creating ROMs and other files in the hex folder, seemed to work for me in MinGW, but I use Windows primarily. Once the ROM files are converted to VHDL, run the ladybug_papilio.xise project in the top directory and synthesize then upload to your board. You need a Papilio Pro with a Arcade Megawing and a PS2 keyboard in port "PS/2 B", VGA and audio connected. Enjoy! This post has been promoted to an article
  6. Hi There, Currently I have been set this project, I am really struggling with how to get going with it. If anyone can assist I would be greatly appreciated. It was a year since I have completed any work in VHDL. If anyone can assist we have been provided with PS2_DISPLAY.vhd, PS2_EXP.ucf, utils.vhd, VHDL_Template_entity.vhd, VHDL_Template_TB.vhd All files are below any help is greatly appreciated! Please assist, thanks in advance. Regards PS2_DISPLAY.vhd utils.vhd VHDL_Template_Entity.vhd VHDL_Template_TB.vhd MiniProject_15.doc PS2_EXP.zip
  7. I'm trying to build the ./bscan_spi_xc6slx9.bit file from source, to program the flash on my Papilio Pro board. From the git source, the only .v or .vhdl source file for Spartan 6 is: ./xc3sprog/trunk/bscan_spi/bscan_s6_spi_isf_ext.v Is this the one I should use? Then for the User Constraints File, the only relevant one I can find is the generic one, The two files obviously don't match, so I from the .ucf file I removed everything except the FLASH_* lines. And in the .v file, I replaced all the MOSI/MISO lines with the FLASH_SI/SO etc lines, like: module top ( output wire FLASH_SI, //MOSI, output wire FLASH_CS, //CSB, output wire FLASH_CK, //DRCK1, input FLASH_SO //MISO ); (and all other places) The resulting .v & .ucf files do generate a bscan .bit file, but when I use that to program the flash, I get this: ./papilio-prog -f ../Helper_App/Quickstart-Papilio_One_LX9-v1.5.bit -b ~joostje/VHDL/bscan-Papilio/top.bit -v Using built-in device list JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9 Uploading "/home/joostje/VHDL/bscan-Papilio/top.bit". DNA is 0xb9c95021930a5ffe Done. Programming time 547.0 ms Programming External Flash Memory with "../Helper_App/Quickstart-Papilio_One_LX9-v1.5.bit". Uknown Flash Manufacturer (0x00) Error: SPI Status Register [0x00] mismatch (Wrong device or device not ready).. Error occured. USB transactions: Write 178 read 10 retries 8 Using the original bscan_spi_xc6slx9.bit does work: As for the reason why I want to build the source (apart from "I should be able to"), I'm using a modified Papilio board design with a Spartan XC6SLX16 (256 pin BGA), So I need to generate a new bitfile for that XC6SLX16. So, doesn anyone know where the .v or .vhdl source files (preferably with a .ucf file) are that can generate a .bit file for the Spartan 6 (Papilio Pro)? Papilio-Loader source was this morning cloned from here: https://github.com/GadgetFactory/Papilio-Loader.git (I've attached my modified .ucf and .v files, both renamed to .txt as the uploader didn't like my .ucf extention) Thanks, joost BPC3011-Papilio_Pro-general.txt bscan_s6_spi_isf_ext.txt
  8. Intro To Spartan FPGA Book

    Version

    232 downloads

    Learn VHDL with Mike Field's free book written specifically for the Papilio and LogicStart MegaWing. Step by step examples and full source code walks you through using all the peripherals on the LogicStart. Mike Field wrote a great ebook to help beginners learn VHDL and FPGA technology. We asked Mike what would be the perfect hardware for his proposed book and the end result was the LogicStart MegaWing! Find all code examples on the ebook's github repository. Wiki page with more material that pre-dates the book. Github page
  9. Hi there, I have downloaded my bit design file to the LogicStart MegaWing as per the book IntroToSpartanFPGABook.pdf. The design is very simple, it is the one in page 15, and since I am using the papilio pro, I am using the following definitions for the ports for led_0,led_1 and switch_0 and switch_1: NET switch_1 LOC = "P115" | IOSTANDARD=LVTTL;NET switch_0 LOC = "P114" | IOSTANDARD=LVTTL;NET LED_1 LOC = "P124" | IOSTANDARD=LVTTL;NET LED_0 LOC = "P123" | IOSTANDARD=LVTTL; I have also successfully added the "Hello World" bit file which works fine on the papilio pro but the bit file that I have generated does not seem to be working with LogicStart MegaWing. After I download the bitfile I get the following:JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9Created from NCD file: Switches_LEDs.ncd;UserID=0xFFFFFFFFTarget device: 6slx9tqg144Created: 2014/03/14 23:29:14Bitstream length: 2724832 bits Uploading "X:\fpga_workspace\test\switches_leds.bit". DNA is 0x398581f20cf18efeDone.Using devlist.txtProgramming time 765.0 msUSB transactions: Write 175 read 7 retries 0 I also see, the first 3 character displays enabled; is this normal?Can anyone help?Thanks,David switches_leds.bit
  10. Often for debugging purposes in a live system I need to display internal states on a seven segment display. This is trivial when I only need to display hex numbers but recently I needed the value represented in decimal because it made more sense for my application. I had a need for a hex to dec converter and as I usually do, I google it first, in case it had been done already. Sure enough, someone has, and the solution involves only shifting and adding 3. The method involved was new to me as I hadn't heard of this way of converting hex to dec, but it works, see his blog. Hope I taught some of you something today
  11. I'm a long time computer programmer and electrical engineer who is just now trying to understand VHDL and FPGAs. I've got some conceptual hurdles I need to get over before I attempt my first design. Probably everyone who is in this field has had these same questions at some point but I could not find the answers by searching the Internet. I'll illustrate my questions with the following VHDL code snippet: entity ENTITY is port ( … ); end entity; architecture rtl of ENTITY is signal instruction : std_logic_vector( 15 downto 0 ); signal is_alu : std_logic; begin process1 begin line 1; line 2; … end process1; is_alu <= ( instruction(15 downto 13 ) = B"011" ) ; process2 begin if (is_alu ) then …. … end process2; end; I understand that within a process block the lines of code are executed sequentially. And I think I understand that any assignments made to signals within a process block aren't actually visible until the process block has finished (goes into a wait). Is this true? My other questions are: 1. Do the two process block run in parallel? 2. Does any code within an entity definition get executed except within a process block? 3. For example, is the is_alu signal assignment shown between the two process blocks actually only evaluated when it is referenced in process2 block? 4. Are there any interactions between the process blocks other than those the code I write cause? 5. If process blocks run totally independently and in parallel how does one guarantee ordered execution of the resultant hardware? This is where I'm definitely missing something and it is probably because of my programming background. 6. Is there some rule of thumb about the type and/or scope of the functionaliy contained in a process block? I'm sure I'll have many more questions but getting answers to these will help alot. Thanks in advance Craig Lindley