Search the Community

Showing results for tags 'SDRAM'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • Community
    • Gadget Factory Reboot 2022-2023
    • Gadget Factory
    • Documentation
    • FPGA Discussions
    • Community Projects
  • Soft Processors
    • Migen/LiteX/Risc-V
    • ZPUino
    • J1 Forth
    • AVR8 Soft Processor
  • Electronics
    • Modules
  • Papilio Platform (Retired)
    • Papilio General Discussion
    • Papilio Pro
    • Papilio One
    • Papilio DUO
    • Papilio Wings
    • DesignLab IDE
    • DesignLab Libraries
    • RetroCade Synth
    • Papilio Arcade
    • Papilio Loader Application
    • Papilio Logic Sniffer
    • Pipistrello
    • Retired
  • Open Bench (Retired)
    • Open Bench Logic Sniffer at Dangerous Prototypes
    • OpenBench Logic Sniffer at Gadget Factory
  • GadgetBox Universal IoT Hardware (Retired)
    • GadgetBox General Discussion
  • Gadget Factory Internal Category

Categories

  • Papilio Platform
    • Papilio One
    • Papilio Plus
    • Papilio Wings
    • LogicStart MegaWing
    • ZPUino
    • Papilio Pro
  • Papilio Arcade
  • RetroCade Synth
  • Logic Sniffer
  • FPGAs
  • DesignLab
    • Example Projects
    • Libraries

Categories

  • Papilio FPGA
    • Papilio UCF (User Constraint) Files
    • Papilio Bit Files
  • Papilio Arcade
  • RetroCade Synth
  • General
  • Beta (Test) Releases
  • Books

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 4 results

  1. Hello Guys, I am working on a verilog memory controller and have a question about the actual model of the SDRAM chip, my question comes because the physical chip says that it is a MT48LC4M16A2 from micron (which have 12 pin address bus width), but after checking on papillio pro's hardware guide there is a schematic that says the memory model is a MT48LC64M4A2 (this one have 13 pin address bus width). Also when downloading the generic UCF file from gadget factory website, there are 13 address pins defined there. I was wondering for which memory model should I design? On the other hand, if memory is MT48LC4M16A2 what is the 13th address on the UCF file mapped to? Thank you
  2. Hello, I'm a newbie in the FPGA, and I'm managing with the Papilio Pro Board. The problem is I can't make the SDRAM work correctly. I was trying to use the Hamster's SDRAM controller, and did as he describes, but I get weird results. First, sometimes it reads with random mistakes (though it might be a write problem, I don't know) Second, sometimes during sequential read it reads first 3-4 values the same and only then starts to increment address. Could you please advise some VHDL code example of how to explore the Hamster's SDRAM controller (or any other)? Hamsterworks wiki site doesn't work for some reason so I can't read his explanation once more... Kind regards, Sergey
  3. Hello Can i replace papilio pro's original SDRAM with something like samsung's K4S561632? as i checked, they are pin to pin compatible.
  4. Hi all, Please, apologies for my bad English. I am building a clone of a ZX Spectrum computer. It was a Zilog Z80 based computer with some custom hardware for video displaying very popular here in Spain in the 80s. I already have a basic working implementation using FPGA's BRAM. Using an ArcadeMegawing it displays a VGA video signal, reads a PS/2 keyboard, plays audio and also, with a simple adapter, can load game from tapes. Since I have already used all available BRAM but I need more to implement some other things (DivMMX emulation, a way to load games from a SD card), I need to use the SDRAM chip onboard. I have read about using SDRAM like if it was SRAM in other topic in this forum. There is said it is possible but only at slow speeds. No problem then because mi clone runs at 3.5 MHz. I am figuring how to use Hamster's SDRAM controller but I am having no success on it. I have wrote this small module to test reading/writing to SDRAM. It writes an incremental value and then reads it. I use the LEDs to see if it is working. I know that the module goes through all three states (send write command, send read command, wait to data is retrieved... then repeat for every memory address) because if I tie LEDs to address signals they display appropriate data (or at least I think they lit as they should, some kind of binary count) but if I tie the LEDs to the read data signal they are always on. I don't know what is wrong with this. Any help is appreciated. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;entity top is port ( netCLK : in std_logic; -- netLED : out std_logic_vector( 3 downto 0); -- sdramCLK : out std_logic; sdramCKE : out std_logic; sdramCS : out std_logic; sdramRAS : out std_logic; sdramCAS : out std_logic; sdramWE : out std_logic; sdramBA : out std_logic_vector( 1 downto 0); sdramADDR : out std_logic_vector(12 downto 0); sdramDQM : out std_logic_vector( 1 downto 0); sdramDATA : inout std_logic_vector(15 downto 0) );end;architecture behavioral of top is signal clock : std_logic; signal ready : std_logic; signal enable : std_logic := '0'; signal wr : std_logic; signal a : std_logic_vector(20 downto 0); signal di : std_logic_vector(31 downto 0); signal do : std_logic_vector(31 downto 0); signal dr : std_logic; signal addrwr : std_logic_vector(20 downto 0) := (others => '0'); signal addrrd : std_logic_vector(20 downto 0) := (others => '0'); signal datawr : std_logic_vector(31 downto 0) := (others => '0'); signal datard : std_logic_vector(31 downto 0); type statetype is (sendwrite, sendread, waitread); signal state : statetype := sendwrite;begin netLED <= datard(23 downto 20);-- netLED <= addrrd(20 downto 17); process(clock) begin if rising_edge(clock) then if enable = '1' then enable <= '0'; else case state is when sendwrite => if ready = '1' then enable <= '1'; wr <= '1'; a <= addrwr; di <= datawr; addrwr <= addrwr+1; datawr <= datawr+1; state <= sendread; end if; when sendread => if ready = '1' then enable <= '1'; wr <= '0'; a <= addrrd; state <= waitread; end if; when waitread => if dr = '1' then datard <= do; addrrd <= addrrd+1; state <= sendwrite; end if; end case; end if; end if; end process; Uclock : entity work.clock port map ( i => netCLK, o => clock ); Usdram : entity work.sdram_controller generic map ( sdram_address_width => 22, sdram_column_bits => 8, sdram_startup_cycles => 10100, cycles_per_refresh => (64000*100)/4196-1 ) port map ( clk => clock, reset => '0', -- interface to issue reads or write data cmd_ready => ready, cmd_enable => enable, cmd_wr => wr, cmd_address => a, cmd_byte_enable => "1111", cmd_data_in => di, data_out => do, data_out_ready => dr, -- sdram signals SDRAM_CLK => sdramCLK, SDRAM_CKE => sdramCKE, SDRAM_CS => sdramCS, SDRAM_RAS => sdramRAS, SDRAM_CAS => sdramCAS, SDRAM_WE => sdramWE, SDRAM_BA => sdramBA, SDRAM_DQM => sdramDQM, SDRAM_ADDR => sdramADDR, SDRAM_DATA => sdramDATA );end;