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Found 6 results

  1. Hello Can i replace papilio pro's original SDRAM with something like samsung's K4S561632? as i checked, they are pin to pin compatible.
  2. Hi all, Please, apologies for my bad English. I am building a clone of a ZX Spectrum computer. It was a Zilog Z80 based computer with some custom hardware for video displaying very popular here in Spain in the 80s. I already have a basic working implementation using FPGA's BRAM. Using an ArcadeMegawing it displays a VGA video signal, reads a PS/2 keyboard, plays audio and also, with a simple adapter, can load game from tapes. Since I have already used all available BRAM but I need more to implement some other things (DivMMX emulation, a way to load games from a SD card), I need to use the SDRAM chip onboard. I have read about using SDRAM like if it was SRAM in other topic in this forum. There is said it is possible but only at slow speeds. No problem then because mi clone runs at 3.5 MHz. I am figuring how to use Hamster's SDRAM controller but I am having no success on it. I have wrote this small module to test reading/writing to SDRAM. It writes an incremental value and then reads it. I use the LEDs to see if it is working. I know that the module goes through all three states (send write command, send read command, wait to data is retrieved... then repeat for every memory address) because if I tie LEDs to address signals they display appropriate data (or at least I think they lit as they should, some kind of binary count) but if I tie the LEDs to the read data signal they are always on. I don't know what is wrong with this. Any help is appreciated. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;entity top is port ( netCLK : in std_logic; -- netLED : out std_logic_vector( 3 downto 0); -- sdramCLK : out std_logic; sdramCKE : out std_logic; sdramCS : out std_logic; sdramRAS : out std_logic; sdramCAS : out std_logic; sdramWE : out std_logic; sdramBA : out std_logic_vector( 1 downto 0); sdramADDR : out std_logic_vector(12 downto 0); sdramDQM : out std_logic_vector( 1 downto 0); sdramDATA : inout std_logic_vector(15 downto 0) );end;architecture behavioral of top is signal clock : std_logic; signal ready : std_logic; signal enable : std_logic := '0'; signal wr : std_logic; signal a : std_logic_vector(20 downto 0); signal di : std_logic_vector(31 downto 0); signal do : std_logic_vector(31 downto 0); signal dr : std_logic; signal addrwr : std_logic_vector(20 downto 0) := (others => '0'); signal addrrd : std_logic_vector(20 downto 0) := (others => '0'); signal datawr : std_logic_vector(31 downto 0) := (others => '0'); signal datard : std_logic_vector(31 downto 0); type statetype is (sendwrite, sendread, waitread); signal state : statetype := sendwrite;begin netLED <= datard(23 downto 20);-- netLED <= addrrd(20 downto 17); process(clock) begin if rising_edge(clock) then if enable = '1' then enable <= '0'; else case state is when sendwrite => if ready = '1' then enable <= '1'; wr <= '1'; a <= addrwr; di <= datawr; addrwr <= addrwr+1; datawr <= datawr+1; state <= sendread; end if; when sendread => if ready = '1' then enable <= '1'; wr <= '0'; a <= addrrd; state <= waitread; end if; when waitread => if dr = '1' then datard <= do; addrrd <= addrrd+1; state <= sendwrite; end if; end case; end if; end if; end process; Uclock : entity work.clock port map ( i => netCLK, o => clock ); Usdram : entity work.sdram_controller generic map ( sdram_address_width => 22, sdram_column_bits => 8, sdram_startup_cycles => 10100, cycles_per_refresh => (64000*100)/4196-1 ) port map ( clk => clock, reset => '0', -- interface to issue reads or write data cmd_ready => ready, cmd_enable => enable, cmd_wr => wr, cmd_address => a, cmd_byte_enable => "1111", cmd_data_in => di, data_out => do, data_out_ready => dr, -- sdram signals SDRAM_CLK => sdramCLK, SDRAM_CKE => sdramCKE, SDRAM_CS => sdramCS, SDRAM_RAS => sdramRAS, SDRAM_CAS => sdramCAS, SDRAM_WE => sdramWE, SDRAM_BA => sdramBA, SDRAM_DQM => sdramDQM, SDRAM_ADDR => sdramADDR, SDRAM_DATA => sdramDATA );end;
  3. Hi, I am new to the papilio enviro and to FPGA's ... (still expecting the 1st delivery) In good preparation of my plans with this device I studied alot opn the subject for a few weeks now and and read around in the existing forums. I started messing with VHDL in xilinx ISE .. The concept of FPGA's has attracted me much, but off course there is a lot to learn still .. I was wondering if it would be possible to used these wonderful 8 megs of SDRAM as video memory for VGA output .. ? If yes ... is it then possible to spilt it up and use the leftover as system RAM for some processor soft core (i was thinking of the 65816 because i have a past in that family) ? Or even better like putting it all in one flat address map where the soft core processor can manipulate the video memory direct random adressable ? I understand that access is limited by time slots .. but in burst modes you can do bulk transfers at high speeds .. but there must be alignment with read and write actions between the constant data refresh cycles ... I have seen the modules for testing the sdram .. but diving into that project in ISE is not a good start for beginners maybe since i did not really find a clear interface how to talk to the SDRAM controller module and translating it somehow into a flat always accesible way like the way you use SRAM.... Are there any experts who can elaborate a little more on this ? Grx.. Eric
  4. Hello Guys, I am working on a verilog memory controller and have a question about the actual model of the SDRAM chip, my question comes because the physical chip says that it is a MT48LC4M16A2 from micron (which have 12 pin address bus width), but after checking on papillio pro's hardware guide there is a schematic that says the memory model is a MT48LC64M4A2 (this one have 13 pin address bus width). Also when downloading the generic UCF file from gadget factory website, there are 13 address pins defined there. I was wondering for which memory model should I design? On the other hand, if memory is MT48LC4M16A2 what is the 13th address on the UCF file mapped to? Thank you
  5. Hi everyone, I am working on a PAL Composite Video generator, and with color bars (no frame buffer), it works great. Now I am at the point that I need a frame buffer, and since the internal memory of the Spartan-6 would never be enough for a full 720x288x3 pixel frame buffer, I hoped to be able to use the SDRAM for this. I have tried, but the results are very bad. I think it is not fast enough or something. I used hamsters SDRAM controller. Is it possible to use the SDRAM as a frame buffer, and is it fast enough? The process that needs the data (RGB->YUV conversion), runs at 50 MHz, but I think it should be possible to do this at 12.5 MHz aswell. According to hamsters wiki, the data should be available at the next clock cycle. But at the top of the controller file, stands that it may take 16 cycles. I don't know if this is enough information, but I hope someone can help me with this. Edit: Here is a capture of the color bars.
  6. Just like to share with you guys an overview of a typical block transfer from the SDRAM. This is used by the ZPUino instruction cache and (for version 2) also the DMA channel. This goes as fast as possible can go. The wishbone data interface witdh is 32-bit, and the SDRAM is 16-bit, so it takes 2 cycles to grab the whole 32-bit word from the SDRAM. In this image we can see the wishbone starting a cycle (asserting the CYC signal), and strobing an address (by asserting the STB signal). If you look more clearly (you cannot see the whole address value here), right after strobing the first address, the STALL signal from the sdram controller is asserted. At this point, the system already has a new address on the bus, and will hold it there until the STALL signal from the controller goes low again. It then proceeds to the next address. This up to the point that there are no more addresses to place on the bus, where the master lowers the STB signal, but it keeps the CYC signal on. Right after the first address strobe, the SDRAM starts to receive the requests. They are also bursted, so you see that addresses are changing even before the first reply from the SDRAM (just after the first high-z period, the longer one on the DQ line). Again, we pipeline even at the SDRAM level, not only at the wishbone level. When the first data starts to come out, you can see the ACK signal from the controller, signaling that data is valid. We keep on getting an ACK each 2 clock cycles until we have read everything we bursted into the SDRAM controller, after which the master lowers the CYC signal, relinquishing the SDRAM for other masters that may exist. A closer look: Here you can see the start of the transaction, with the proper values filled in. Notice how the clock and the SDRAM lines are not aligned: this takes all the IO delays into account. Alvie