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Found 2 results

  1. Hi, I wonder how the access to the on-board RAM can be implemented and organized. So far I know that a ZPUino uses the on-board RAM to store programs and data. If I understand it correctly, the ZPUino implementation uses the sram_ctl8.vhd source to access the RAM chip via a Wishbone bus interface. I want to use the Papilio DUO to simulate an expansion board for an old 6502-based computer (Ohio Scientific Challenger 1P). On the one hand I want to use a part of the Papilio DUO RAM chip as a memory expansion for the 6502 board. On the other hand a floppy controller with attached floppy disks shall be simulated with storage on an SD card. So for the RAM expansion alone I only need to translate the 6502 bus to something that can communicate with the Papilio DUO's RAM chip. I either could create a Wishbone bus wrapper around the 6502 bus, and use the sram_ctl8.vhd as-is, or I could directly build a bridge from the 6502 bus to the RAM chip based on the internals of the sram_ctl8.vhd source. But when the floppy controller comes into the picture it gets more complicated. I need to simulate some of the chips for the floppy controller (6850 ACIA and 6820 PIA) and map them into the address space of the 6502. For access to an SD card I will either need to use a ZPUino or the real ATmega32U4 processor. With a ZPuino I would need to divide the RAM between the memory expansion and the ZPUino. So lots of questions arise: How can I divide the RAM between the ZPUino and other parts of my design? Could that be managed with compile and link time options when building the sketch for the ZPUino, or would I need to build something in VHDL? Is it even possible at all to influence the ZPUino's use of the RAM chip without modifying its implementation? Would it be better to use the ATmega32U4 for implementing the access to the SD card? I'm obviously at the very beginner level regarding designing and implementing such a project, so I would be very grateful about any tips and experiences in this area. Thanks Stephan
  2. Hi, I'm new to FPGA programming. I'm interested in the Papilio DUO and I have some general technical questions. I have an old 6502-based computer (Ohio Scientific Challenger 1P). The project that I'm thinking of is to build a floppy controller with simulated floppy drives. An SD card would be used to provide the floppy storage. I would also like to implement a 32 kB RAM expansion for the machine. My first question is, would the Papilio DUO be an appropriate platform for this kind of project? The FPGA would need to provide the logic that on the real board was implemented with an 6820 and 6580 chip and additional TTL logic chips. To avoid any confusion, I'm talking here about 1980's technology, where the CPU was clocked with 1 MHz. The second question is, how exactly can the 512 kB or 2 MB RAM of hte Papilio DUO be used? Is the RAM exclusively needed for storing the logical configuration of the FPGA, or could it also be used to store data, and the FPGA makes it look like RAM to the 6502 CPU? Thanks for your time Stephan