Search the Community: Showing results for tags 'Papilio Pro'.

More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • GadgetBox Universal IoT Hardware
    • GadgetBox General Discussion
  • Papilio Platform
    • Papilio General Discussion
    • Papilio Pro
    • Papilio One
    • Papilio DUO
    • Papilio Wings
    • DesignLab IDE
    • DesignLab Libraries
    • RetroCade Synth
    • Papilio Arcade
    • Papilio Loader Application
    • Papilio Logic Sniffer
    • Retired
  • Electronics
    • Modules
  • Soft Processors
    • ZPUino
    • J1 Forth
    • AVR8 Soft Processor
  • Community
    • Gadget Factory
    • Documentation
    • FPGA Discussions
    • Community Projects
    • Pipistrello
  • Open Bench
    • Open Bench Logic Sniffer at Dangerous Prototypes
    • OpenBench Logic Sniffer at Gadget Factory
  • Gadget Factory Internal Category


  • Papilio Platform
    • Papilio One
    • Papilio Plus
    • Papilio Wings
    • LogicStart MegaWing
    • ZPUino
    • Papilio Pro
  • Papilio Arcade
  • RetroCade Synth
  • Logic Sniffer
  • FPGAs
  • DesignLab
    • Example Projects
    • Libraries


  • Papilio FPGA
    • Papilio UCF (User Constraint) Files
    • Papilio Bit Files
  • Papilio Arcade
  • RetroCade Synth
  • General
  • Beta (Test) Releases
  • Books

Found 19 results

  1. Hello, I've just returned from DConf 2017, in Berlin. There I gave a talk on how to use an extension of the D programming language (DHDL) to design hardware. I showed a demo of Classic Empire, a game written by Walter Bright (the original creator of D), running on a Papilio Pro, inside a soft-core RISC-V CPU, plus my own handmade "wing" IO accessories and respective controller IP blocks (VGA, 7-segment, sound, etc.). You can see a quick demo below: You can also see the full talk, if it sparks your interest: Thanks to the generosity of GadgetFactory, we raffled a Papilio Pro and some accessories to the participants of the talk: Gauging from his reaction, Vang Le was very surprised and happy to be the winner, and he's looking forward to exploring the world of FPGAs. In my demo I loaded the binary code for the game through the USB/UART, using a custom utility. In the next few months I plan to further tweak this demo, so that the game code is loaded from flash and it works with standard GadgetFactory wings. When that is done, I'll provide the bit stream files for the combined hardware design + the game. Walter Bright has indicated that he would provide permission for the FPGA version of the game to be distributed freely, so GadgetFactory could use it for its showcase. Later, I will provide the source code for my whole setup; I used the LDC 2 D compiler with the (old) LLVM RISC-V backend, and I had to workaround a lot of bugs of invalid RISC-V code. When the new LLVM RISC-V backend is released I expect all of that to be alleviated or completely fixed, which will help with the release of the complete demo setup. I'll keep providing updates and feedback here on the GadgetFactory forums. You can also follow me on Twitter (@Luis3m), or email me if you have any questions ( Also, a shout-out goes to Mike Field, whose book / tutorial helped me get started with FPGAs and hardware design. I shared the love for his book with some conference participants :-) So long, Luís
  2. Hi all, over the last half year I have implemented a processor and surrounding SoC bringing the RISC-V ISA ( to the Papilio Pro. It implements the 32Bit integer subset (RV32IM). The project is hosted on Gitub ( It still needs some additional documentation, cleanup and ready-to-run ISE projects to make it easy reproducable for others. But I post this link now, to find out if anybody is interested in my work. I will soon also post a bitstream here so anybody with access to a Papilio Pro can play with it. I have also ported eLua to it @Jack: If you like I can also present the project in the GadgetFactory blog. Regards Thomas
  3. Hello, Do you have a .bit file for the Papilio Pro + LogicStart that plays some audio? Something weird is going on here, and starting with a known good .bit file would help Thanks, Luís
  4. Hi All, I just got my new Papilio Pro and I was trying the examples from DesignLab. I've been playing around with different examples (Audio, VGA, etc.) and they work fine. But when I run any of the VGALiquidCrystal examples thye are just displaying two rows of green squares but no text in there. The following screenshot (LCD_Demo.jpg) shows the results I get from the "LCD_Demo" example. The VGA demos work fine (see screenshot - VGAHelloWorld.jpg) Just fyi, I'm not using any Wing, I'm just connecting 6 pins in the CH Wing2 port to the VGA cable (V-SYNC, H-SYNC, R, G, B, GND) as in the screenshot - DirectPinout.jpg. I am wondering if I am missing anything here. Do I require to connect anything else? Working with a real Liquid Crystal display needs to connect a couple of signals (rs, enable, data, etc.) but is it also necessary in this modified version? If not, what do the pins in the VGALiquidCrystal() call mean? Regards, Andres
  5. I just dusted off my RetroCade MegaWing and wanted to try the 1.3 Synth code, but I'm finding that things don't seem to be compiling in DesignLab. I tried the loading a newer example from GITHUB, and loading the bit file, but it does not get very far. It has been a while since I have used DesignLab, but I recall that I had this working smoothly in the past. That was on an earlier version of DL, and the RetroCade code was 1.1. Has anyone had the same problem using the RetroCade with a Papilio Pro?
  6. I recently purchased a Papilio Pro together with a Logic Start board. Whenever I try to send a compiled example program to the board I get the following error message; Board: GadgetFactory Papilio Pro LX9 @ 96000000 Hz (0xa4041700) Board mismatch!!!. Board is: 0xa4041700 'GadgetFactory Papilio Pro LX9' Sketch is for: 0xb4041700 'GadgetFactory Papilio Pro LX9 (ZPUino 2.0)' My conclusion is that the supplied board has version 1 of the ZPUino installed and not the latest version as I would have expected. How do I install ZPUino version 2.0.
  7. Hi there, I'm on Ubuntu 14.04 and after much faff trying to get my PP to work, I think it is knackered. I get this when programming: Programming to SPI FlashUsing built-in device listCannot find device having IDCODE=00010440Unknown Papilio BoardUsing built-in device listCannot find device having IDCODE=00400400IOException: Cannot open file USB transactions: Write 4 read 3 retries 0Error while burning bitfile. The IDCODE fields seem to be random when I run papilio-prog several times. I assume that means the FTDI is mangling the serial data? Any ideas? I've also got a DUO. Works perfectly with this same setup. I tried installing the linux 'drivers' but these seem to just install libftd2xx which isn't even linked against the papilio-prog (which uses open source libfdti) AND doesn't contain a linux kernel module either so I don't understand their relevance to anything. It does have a libusb in there though. Haven't tried that, get the feeling it's not going to help things.. The default FTDI drivers in Ubuntu work fine after running, with the Duo. Minor note: Think it would be a good idea to remove all references to Spent a while searching the net for this script before discovering somewhere it is now Error msg in DesignLab 1.0.7 still refers to too. Kind Regards,Chris
  8. Hi everybody I'd like to supply the Papilio Pro (with the Retrocade MegaWing) with a battery. Do I have to solder two cables next to the USB port ? Which voltage would you recommand ? 4.5V ? 6V ? 9V ? Thanks
  9. Hi! I am trying to use a Papilio Pro to run a stepper motor since the Teensy, Arduino microcontrollers proved insufficient for my purposes. I am interfacing the Papilio pro with the L6470 IC which is going to be the motor driver. My main problem is this - I am keen on using a Python module to control the stepper motor but I have no clue as to how to go about writing the code for the Papilio Pro which will be the board that will receive the bits sent via the Python code and will reroute it through the IC which will translate that in to stepper motion. The bits here are basically my position, speed values, etc. I have plans for sending entire waveforms, say, to make the motor oscillate between two positions and so on. I was wondering how I should go about this project?
  10. Hi There I had purchased a Papilio Pro a while ago, but didn't get time to play around with it. But recently when I tried to program it with the Quick Start bit file, the programmer couldn't recognize it. Suspecting that the FDTI EEPROM might have corrupted or similar, I switched from Ubuntu to Windows and used the FTDIProg utility to read. It looked non-empty, so I erased it and programmed which I thought is the default configuration. It still didn't help To investigate further, I programmed the FDTI with opto isolators activated and soldered in the JTAG pins. However the impact was unable to recognize the device. Not sure whats going on. Any help will be appreciated. The following is the diagnostic outputs from the programmer : xx:~ (master)> pap-check-status Executing /opt/GadgetFactory/papilio-loader/bin//opt/GadgetFactory/papilio-loader/bin/pap-check-status.... Using built-in device listInvalid chain position 0, position must be less than 0 (but not less than 0). ############################################# Programmer status ############################################ Using built-in device listInvalid chain position 0, position must be less than 0 (but not less than 0). Response incompatible with mask xxxx01ISC_Done = 0ISC_Enabled = 0House Cleaning = 0DONE = 0 ############################################# FPGA Status ############################################ Using built-in device listInvalid chain position 0, position must be less than 0 (but not less than 0). STAT RegisterID_ERROR = 0 IDCODE not validated.DONE = 0 Input from the DONE pin.INIT = 0 Input from the INIT pin.MODE = 000b Input from the MODE pins (M2:M0).GHIGH_B = 0 0 = asserted.GWE = 0 0 = all FFs and Block RAMs are write-disabled.GTS_CFG = 0 0 = all I/Os are 3-stated.IN_ERROR = 0 Legacy input error.DCI_MATCH = 0 DCI is matched.DCM_LOCK = 0 DCMs are locked.CRC_ERROR = 0 CRC error.cycleTCK in TEST_LOGIC_RESET ====================================================================================================================================== With exactly the same setup my Papilio500 works without any problem.The diagnostics produces the following output: 2004 pilakkat@pilakkat-W500:~ (master)> pap-check-status Executing /opt/GadgetFactory/papilio-loader/bin//opt/GadgetFactory/papilio-loader/bin/pap-check-status.... Using built-in device listJTAG chainpos: 0 Device IDCODE = 0x41c22093 Desc: XC3S500E ############################################# Programmer status ############################################ Using built-in device listJTAG chainpos: 0 Device IDCODE = 0x41c22093 Desc: XC3S500E ISC_Done = 1ISC_Enabled = 0House Cleaning = 1DONE = 1 ############################################# FPGA Status ############################################ Using built-in device listJTAG chainpos: 0 Device IDCODE = 0x41c22093 Desc: XC3S500E STAT RegisterID_ERROR = 0 IDCODE not validated.DONE = 1 Input from the DONE pin.INIT = 1 Input from the INIT pin.MODE = 001b Input from the MODE pins (M2:M0).GHIGH_B = 1 0 = asserted.GWE = 1 0 = all FFs and Block RAMs are write-disabled.GTS_CFG = 1 0 = all I/Os are 3-stated.IN_ERROR = 0 Legacy input error.DCI_MATCH = 1 DCI is matched.DCM_LOCK = 1 DCMs are locked.CRC_ERROR = 0 CRC error. More over I am able to connect the XILINX Platform Cable II and use it with impact!!! Regardsskp
  11. An inherited project has the following #includes in main.c: #include <stdio.h> #include <string.h> #include <stdlib.h> #include "xparameters.h" #include "xgpio.h" #include "xio.h" #include "xstatus.h" #include "xuartlite.h" #include "xtmrctr.h" #include "xintc.h" #include "xil_exception.h" ZAP 2.3.0 barfs on the Xilinx #includes: main.c:37:25: error: xparameters.h: No such file or directory main.c:38:19: error: xgpio.h: No such file or directory main.c:39:17: error: xio.h: No such file or directory ... Hardwiring the paths complicated this, as the referenced #includes reference others: #include "/opt/Xilinx/14.7/ISE_DS/EDK/sw/XilinxProcessorIPLib/drivers/gpio_v3_01_a/src/xgpio.h" results in: In file included from main.c:27: /opt/Xilinx/14.7/ISE_DS/EDK/sw/XilinxProcessorIPLib/drivers/gpio_v3_01_a/src/xgpio.h:123:23: error: xil_types.h: No such file or directory /opt/Xilinx/14.7/ISE_DS/EDK/sw/XilinxProcessorIPLib/drivers/gpio_v3_01_a/src/xgpio.h:124:24: error: xil_assert.h: No such file or directory /opt/Xilinx/14.7/ISE_DS/EDK/sw/XilinxProcessorIPLib/drivers/gpio_v3_01_a/src/xgpio.h:125:21: error: xstatus.h: No such file or directory Even if this worked, it is not evident which of the multiple versions of the various *.h files to reference (ppc405, microblaze, ppc440, cortexa9, ...) How are the Xilinx headers to be referenced in a ZAP project? There does not appear to be a place to specify the many directories where these files are located. Which ones should be included for the Papilio Pro?
  12. I'm trying to build the ./bscan_spi_xc6slx9.bit file from source, to program the flash on my Papilio Pro board. From the git source, the only .v or .vhdl source file for Spartan 6 is: ./xc3sprog/trunk/bscan_spi/bscan_s6_spi_isf_ext.v Is this the one I should use? Then for the User Constraints File, the only relevant one I can find is the generic one, The two files obviously don't match, so I from the .ucf file I removed everything except the FLASH_* lines. And in the .v file, I replaced all the MOSI/MISO lines with the FLASH_SI/SO etc lines, like: module top ( output wire FLASH_SI, //MOSI, output wire FLASH_CS, //CSB, output wire FLASH_CK, //DRCK1, input FLASH_SO //MISO ); (and all other places) The resulting .v & .ucf files do generate a bscan .bit file, but when I use that to program the flash, I get this: ./papilio-prog -f ../Helper_App/Quickstart-Papilio_One_LX9-v1.5.bit -b ~joostje/VHDL/bscan-Papilio/top.bit -v Using built-in device list JTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9 Uploading "/home/joostje/VHDL/bscan-Papilio/top.bit". DNA is 0xb9c95021930a5ffe Done. Programming time 547.0 ms Programming External Flash Memory with "../Helper_App/Quickstart-Papilio_One_LX9-v1.5.bit". Uknown Flash Manufacturer (0x00) Error: SPI Status Register [0x00] mismatch (Wrong device or device not ready).. Error occured. USB transactions: Write 178 read 10 retries 8 Using the original bscan_spi_xc6slx9.bit does work: As for the reason why I want to build the source (apart from "I should be able to"), I'm using a modified Papilio board design with a Spartan XC6SLX16 (256 pin BGA), So I need to generate a new bitfile for that XC6SLX16. So, doesn anyone know where the .v or .vhdl source files (preferably with a .ucf file) are that can generate a .bit file for the Spartan 6 (Papilio Pro)? Papilio-Loader source was this morning cloned from here: (I've attached my modified .ucf and .v files, both renamed to .txt as the uploader didn't like my .ucf extention) Thanks, joost BPC3011-Papilio_Pro-general.txt bscan_s6_spi_isf_ext.txt
  13. Sorry about the bad pun...I am taking a computer networking class this term and the teacher has said token ring about 20+ times in 9 class periods. So, I got to thinking about how to implement such a design with logic. I spent today reading Introduction to Digital Design and messing around with the new Aldec Active HDL I had to download (due to the student version expired 1-1-14). I got a token ring simulation working on the PapPro and logic start wing. Each switch represent a network connected to the ring. If the switch is up the network wants to transmit. When the led above the switch is on the network has the token and is transmitting. If the switch is down the token is passed quicker. The token is placed in the ring by the up joystick and pressing the joystick like a button resets the whole ring(without a token). I spent about 8 hours messing with this. It just looks like a glorified Larson scanner though (if all switches are up). Oh well. One interesting thing I learned from it is that if you time it right and put 2 or more tokens into the ring (by pressing up again) and all the switches are not up, one token can catch the other one and it gets destroyed or less often both tokens get destroyed. I don't know if this is how it would work in a real token network since they only have one token, maybe it is just a flaw in my design. I used lots of D flip flops, some pulse extenders and clippers, a clock divider with fast and slow output, and a lot of or and and gates. Check it out if you have the papilio pro, logic shield and papilio loader handy and want to see some flashing leds respond to switches. token_top.bit
  14. I've finally gotten far enough in my project to post some status. The task at hand is to capture (and maybe in the future write) data off of arcane disk formats. In the past I've used the catweasel card, but it is no longer supported, and isn't general purpose enough to support the needs of my current subject, the Compucolor II floppy disk. I turned to the kryoflux card, but soon realized that I didn't like the API much, and I was going to have to build an adapter card, as the CCII floppy interface is nonstandard. Also, some of my past arcane disk decoder projects used an 8" drive, and I would need yet another adapter for those. Since I was going to build an adapter, why not go all in and build my own capture hardware. So I bought my Papilio Pro and got to work. I wrote my own SDRAM controller, but then glommed on to Mike Field's (Hamster's) SDRAM design, before going back to my own. The FPGA work was actually the easy part. Once I was able to capture bits off the disk, I had to write a python script to decode the bits into sectors and tracks and whole disk images, to decode the file structure and detokenize BASIC programs and such. The python script has a mini-shell to allow me to interact with it, eg, if a disk has read errors, I can dump the contents of individual sectors, or ask for specific tracks to retry capture. Anyway, I've posted a 5 minute youtube clip of my setup showing it at work. This is my first attempt at narrating a video and it could be better, but it is good enough for now. I've used this system to capture about 250 disk images for the Compucolor II, and I may come into another large batch to process. PCBs should be showing up in a week or two, then I'm going to rewrite one of my old catweasel drivers (for the wang 2200 computer) to use this new system. This post has been promoted to an article
  15. I have been able to find vhdl projects for an AVR8 core for both the Papilio One 250K and 500K but no such project for the Papilio Pro. I also found a .ucf file for the Papilio Pro. Does anyone know where I can find a Papilio Pro Xilinx project that creates an AVR8 core? It would be a great help!
  16. Hi! I'm new to this, but already hooked on using the Papilio Pro for development. This has led to a list of interesting projects on a list - giving rise to a lot of questions. I have a LogicStart Wing, and could be using the ADC on that. But once a hacker... So I have looked for a software all-digital ADC-solution. The Xilinx site has one somewhere for the Spartan-3. There isn't much mention of it, and the data are for running it explicitly on the Spartan-3, of course. Has anyone out there tried porting the software ADC to Spartan-6/Papilio Pro? Had any succes? Wanting to share the VHDL code? The hardware ADC solution seems to work, but, really: that's no fun!!! My concrete project is a reciever for DCF77 (european time signal on 77,5 kHz). The AM modulation from this is usually decoded with little prefabricated radios. But I would like to do use phase modulation, it also contains. That should enable a faster time to lock. I do have the hardware for giving me the DCF77 signal in a 3.3 V logic format, and could do it that way around. But I'd really like to tinker with the DSP48 slices and do some filtering, thus the need for ADC functionality. I will of course need some AGC in front of the Papilio Pro, as the ADC probably wouldn't have a higher resolution than maybe 14-16 bits. Yours, etc. Peter
  17. (This includes observations and details that may be of use to other new users and those new to the Pro, as well as my own questions to follow.) What I'm using: Papilio Pro v1.3LogicStart MegaWing v1.2Windows 7Xilinx ISE Webpack 14.4 (Xilinx_ISE_DS_Win_14.4_P.49d.3.0 from the Vivado and ISE Design Suites download sub-section)Xilinx Device Pack 2012.4.1 (includes important updates for the WebPack)Papilio Loader-2.4-Setup-noJava (I already have Java)Notes: To the admin: There's a beta 2.0 Loader I stumbled across elsewhere on this site. It appears to be out-of-date.The loader may show an older version on its title bar. I've opened an issue with regard to this but it didn't cause problems for this example.Install the Papilio Loader, the Xilinx WebPack software, and the Xilinx Device Pack. Create the license for the free features of the ISE Design Suite and import that license (which you'll receive via email) to the ISE Design Suite. Open the ISE Design Suite and create a new HDL project with Spartan-6 settings appropriate to the Papilio Pro (Note that "Enable Message Filtering" is optional but useful): (At this point I'm mostly following the Intro to Spartan FPGA book with some important changes.) Add a new source VHDL module. Rather than using the wizard, I pasted in the source for this entity directly from the book (be sure to edit out any cruft if your copy spanned a page-break). Note that the entity name doesn't need to match the module name. Add an Implementation Constraints file (I called mine constraints.ucf). This was a little more tricky, since the pins in the book are for the Papilio One 500K, not the Pro. Retrieve the BPM7003-Papilio-Pro-LogicStart-MegaWing-general.ucf file and use it to find the appropriate pin mappings for the Pro (if you cut-and-paste these from the UCF, be sure to rename them accordingly!) This is what I used: NET SWITCH_0 LOC="P114" | IOSTANDARD=LVTTL; # C0NET SWITCH_1 LOC="P115" | IOSTANDARD=LVTTL; # C1NET LED_0 LOC="P123" | IOSTANDARD=LVTTL; # C8NET LED_1 LOC="P124" | IOSTANDARD=LVTTL; # C9Select the VHD file and you'll see the option in the pane below to "Generate Programming File". Run it. You shouldn't get any warnings or errors for this example. Plug in the Papilio Pro (with the LogicStart wing attached). Ensure the drivers load (it may take a short bit the first time you use it). Start the Loader and select the .bit file you just created in your project area (leave the .bmm and .hex file entries blank). Be sure "SPI Flash" is selected below "Write to". Select "Do Selected Operations" and wait for the programming process to complete successfully (there's troubleshooting info in the book and on the forums here). Try it out! The switches enabled by this module happen to control the LEDs above them. Change things! Swap switch_0 and switch_1 in the architecture section of the design, rebuild and upload again - now the switches control the opposite LEDs. Hopefully you find this quick-start useful! I have some questions which I'll add in the first comment below.
  18. Here is the Papilio Pro User Guide. Watch for the Papilio Pro to be available in the Seeed Studio Store tomorrow for $84.99. Jack.
  19. Version 1.1


    The Papilio Pro board implements SDRAM instead of SRAM. It also has switching voltage regulators which means no heat will be generated on the board. This board is still in prototype stage.