Search the Community: Showing results for tags 'MAX5556'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • GadgetBox Universal IoT Hardware
    • GadgetBox General Discussion
  • Papilio Platform
    • Papilio General Discussion
    • Papilio Pro
    • Papilio One
    • Papilio DUO
    • Papilio Wings
    • DesignLab IDE
    • DesignLab Libraries
    • RetroCade Synth
    • Papilio Arcade
    • Papilio Loader Application
    • Papilio Logic Sniffer
    • Retired
  • Electronics
    • Modules
  • Soft Processors
    • ZPUino
    • J1 Forth
    • AVR8 Soft Processor
  • Community
    • Gadget Factory
    • Documentation
    • FPGA Discussions
    • Community Projects
    • Pipistrello
  • Open Bench
    • Open Bench Logic Sniffer at Dangerous Prototypes
    • OpenBench Logic Sniffer at Gadget Factory
  • Gadget Factory Internal Category

Categories

  • Papilio Platform
    • Papilio One
    • Papilio Plus
    • Papilio Wings
    • LogicStart MegaWing
    • ZPUino
    • Papilio Pro
  • Papilio Arcade
  • RetroCade Synth
  • Logic Sniffer
  • FPGAs
  • DesignLab
    • Example Projects
    • Libraries

Categories

  • Papilio FPGA
    • Papilio UCF (User Constraint) Files
    • Papilio Bit Files
  • Papilio Arcade
  • RetroCade Synth
  • General
  • Beta (Test) Releases
  • Books

Found 1 result

  1. Hello. I'm working on a MAX5556 Audio DAC Wing and I thought I should share it here . It (obviously) has a MAX5556 Stereo DAC at its core, with an I2S-compatible interface and up to 50KHz sampling rate (perfect for standard 44.1 and 48 KHz sampling rates) and a resolution of 16 and 24 bits. The board does not contain any output buffer as I wanted the board to be as small as possible. It only has the MAX5556, a couple of passives and a 3.5mm stereo jack. I'll leave you with the schematics and a render of the board. Any criticism is well accepted I'm also prototyping a Megawing with an ADC, a DAC and an Ethernet controller to stream audio over ethernet. Schematic.pdf