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Found 2 results

  1. Hi, I am trying out the newbie example here: http://papilio.cc/index.php?n=Papilio.GettingStartedISE (plan to load design onto a Papilio One 250) Running synthesis gives this error: Starting Placer Phase 1.1 ERROR:Place:311 - The IOB clk is locked to site IPAD21 in bank 0. This violates the SelectIO banking rules. Other incompatible IOBs may be locked to the same bank, or this IOB may be illegally locked to a Vref site. ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed. The constraint file (downloaded from here) NET clk LOC="P89" | IOSTANDARD=LVCMOS25 | PERIOD=31.25ns; When I change the IO type to IOSTANDARD=LVCMOS33, PnR completes without error. What could be the reason why 2.5V CMOS is not supported? Thanks Anirban
  2. So after installing that huge obsolete Xilink ISE WebPack Design tools which is what was needed to edit circuits for the Spartan 6 FPGA on the Papilio Pro, I went on to open the DesignLab IDE, click on new circuit, and then edit circuit to create and edit a new schematic when I get this error. The clicking of the edit button should have opened the ISE project navigator like in one these videos (https://www.youtube.com/watch?v=XHhU5JiKdUY) that show how to go about making FPGA circuits using the IDE. I am instead getting this error (see attachment), can anybody guess why? I have tried running the program as admin and I will try reinstalling the IDE, but I think the problem lies elsewhere.