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Everything posted by keesj

  1. data_valid pattern?

    FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version (chaper 7.2.4) talks about Interface circuits and using one of the following methods A flag FF (Flip Flop) A flag FF and a one word buffer A Fifo buffer To solve this problem
  2. data_valid pattern?

    Hello, I am starting on my first real project and trying to find a good example of signaling. Many examples I see create a component that does something similar to what is listed bellow in clk in data[8] in data_valid process (clk) state machine when idle => if data_valid change state to blabla when blabla => do stuff Basically a "data_valid" or similar is used to start the process. I am wondering how it normally is prevented that the state machine is not run multiple times(if the signal does not change) or and It there a way to enforce the "data_valid" signal to be low before we start the next iteration or is this somehow not necessary and I am missing something ?
  3. Hi, I stumbled up on this (ratter long but interesting video on "icesoc" ) I might give us some ideas
  4. Hi, I am based in the Netherlands and want to order a few parts (Papilio pro, some wings and io buffers). What is the best plat to order the items? When I order from the US I normally have to pay additional handling fees and I would like to avoid this I don't mind waiting a few day before getting the stuff I have seen a few places that offer the hardware (sparkfun, seedstudio,this website) can anybody recommend where to get the hardware?
  5. SPI MODE0

    Hi, I am trying to interface with an 8x8 Led-Digit driver. I Started by bit banging the code to get something working void send(int value) { // enable CS digitalWrite(MX_CS, LOW); w(); int v = value; for (signed int x = 15; x >= 0; x--) { digitalWrite(MX_DATA, ((v >> x) & 0x1) ? 1 : 0); w(); digitalWrite(MX_CLK, HIGH); w(); digitalWrite(MX_CLK, LOW); w(); } digitalWrite(MX_CS, HIGH); w(); } Next I moved to using the zpuino SPI block. I looked at the datasheet above and the wikipedia article on SPI and determined I need to send my SPI message using "MODE0". When I do so the SPI device is not working properly And from looking at the SPI implementation I think the problem is that the values are always set on the rising edge of the clock while for MODE0 the value should be set before (e.g. on the falling edge). Am I missing something? (from experimenting using MODE2 apprears to work but then clock stays high in between cycles) Here is my setup (for the fun o it): I hoped to be able to use a pin of the IO BufferWing to be able to drive the display but this did not work.
  6. Hi, What for for me currently is to open a project e.g. ZPUino multiple serial ports and add the component (e.g. spi) and start modifying it but I am not 100% sure this is the right way to create a clean library
  7. Hi, I am trying to modify the standard Wishbone peripherals. Here is what I did I cloned the git repository containing the DesignLab examples, renamed my local libraries to libraries-old and configured the ide to use DesignLab_Examples as Sketchdir.(it llook like the examples directory might also need a rename) Next using the file open I go to libraries/ZPUino_Wishbone_Peripherals and open the "edit_library.ino" in that folder. Next I clicked on the sketchdir://Chip_Designer.xise to open the ISE. This opens the ISE editor. For this example the editor open with an error that it can not find AUDIO_zpuino_wb_pokey.vhd So I started seaching for that file and found it in a different folder where I found a similar project For short DesignLab_Examples/00.Papilio_Schematic_Library/Libraries/Wishbone_Peripherals and DesignLab_Examples/libraries/ZPUino_Wishbone_Peripherals Are similar but different. The Wishbone_Peripherals is lacking a project file and the ZPUino_Wishbone_Peripherals is lacking a vhd file. How am i supposed to modify the library?
  8. Papilio Pro still produced?

    Currently you can get them for cheap at seeed studio:
  9. SPI MODE0

    Hi, I started looking into the code to try and understand the problem myself. the SPI master does have enough flags passed to the code e.g. spi_samprise is kinda taken into account to determine when to sample the signal (at rise or fall of the clock) and (I think sets the do_sample correctly) However Will alway shift on the rising edge of the spi clock. I made small modifications trying to fix it but I am getting into trouble because I need to skip the first rising edge e.g. if try to I skip the first rising edge all my data if off by one clock cycle.
  10. Hi, Yesterday I started playing with the sump logic analyzer code on the Papilio Pro. I took the basic example and started modifying the system to add an additional serial port and started sniffing that serial port. In my sketch I added some serial.write and everything works as expected until I start writing 4 bytes to the serial e.g not "kee" but "kees". At that point OLS no longer works. any hints what is going on? In the attached picture you can see that the serial.write actually takes some time from the CPU to execute is this blocking the wishbone bus or something similar causing the Logic analyzer to stop working? I am using ols- My goal is to be able to "trigger" on a certain UART character or other events on the system. I plan on glueing the SUMP with the UART or other blocks. Is the current code in the IDE the best one to follow or should I base the code on the new whishbone based interface?. I have had more little problems: In OLS I can not configure the system to use 1 bank e.g. 8 bits as the SUMP code currently always sends 16 bits/2 bytes I would be interested in accessing the SUMP data over a different port from the UART (possibly JTAG or a different port) but the jtagserver is not ported to linux It looks like RLE is not working (kinda documented but not very clear what the status is)
  11. Well the behavior is that the capture never completes. One small modification I did that appeared to improve a little was replacing the if(serial.available) by while(serial.available). I will perform more tests(also try @bnusbick's suggestion.
  12. Yea it looks like there is no place to order the Papilio pro from the EU(out of stock)
  13. Hi, I am sure is it documented somewhere but what is the best way to modify existing library items? I am currently making the modifications in opt/DesignLab-1.0.8/libraries but this tends to break my other designs.
  14. Modifying the libraries

    That sounds like a good plan
  15. CaseSensitive bit

    Hello, I am using DesignLab 1.0.8 under Linux and I have a small problem when generating new bit files. The problem is that the case of the files is different from the default and therefore the IDE won't flash my new file. I either need to rename the file or create a symlink. For example the Multiple_Serial_Ports example Creates a Papilio_Pro.bit file while the IDE expects papilio_pro.bit. With kind regards
  16. Hi, I tried registering to the forum with a new (work) account but this currently fails. I am not getting the confirmation email.
  17. Hi, The same applies to ubuntu 16.10.I suggest upgrading to ols- (for java 1.8 support)
  18. ZPUino HDL Source Code

    The zip as posted (sha556 fe10bd54b6f01939d68df776484383f647c00987aad256aa9a5fe77b1d5caa05 ../../ files does currently not extract properly under Linux keesj@700z:~/Downloads/tmp/zp$ unzip ../../ Archive: ../../ 971a1459607f23e6b9814e444df8716ee877de98 extracting: ZPUino-HDL-Source-V1.0 checkdir error: ZPUino-HDL-Source-V1.0 exists but is not directory unable to process ZPUino-HDL-Source-V1.0/.gitignore. checkdir error: ZPUino-HDL-Source-V1.0 exists but is not directory unable to process ZPUino-HDL-Source-V1.0/.project. checkdir error: ZPUino-HDL-Source-V1.0 exists but is not directory unable to process ZPUino-HDL-Source-V1.0/Papilio/. checkdir error: ZPUino-HDL-Source-V1.0 exists but is not directory .. .. checkdir error: ZPUino-HDL-Source-V1.0 exists but is not directory unable to process ZPUino-HDL-Source-V1.0/zpu/sw/startup/time.c. I found a workaround for the first problem by adding the path to be extrated but still there are some errors unzip ../../ ZPUino-HDL-Source-V1.0/* keesj@700z:~/Downloads/tmp/zp$ unzip ../../ ZPUino-HDL-Source-V1.0/* Archive: ../../ 971a1459607f23e6b9814e444df8716ee877de98 inflating: ZPUino-HDL-Source-V1.0/.gitignore inflating: ZPUino-HDL-Source-V1.0/.project creating: ZPUino-HDL-Source-V1.0/Papilio/ creating: ZPUino-HDL-Source-V1.0/Papilio/papilio_one_250k_vanilla_ise/ inflating: ZPUino-HDL-Source-V1.0/Papilio/papilio_one_250k_vanilla_ise/papilio_one_250k_vanilla_ise.xise creating: ZPUino-HDL-Source-V1.0/Papilio/papilio_one_500k_vanilla_ise/ inflating: ZPUino-HDL-Source-V1.0/Papilio/papilio_one_500k_vanilla_ise/papilio_one_500k_vanilla_ise.xise creating: ZPUino-HDL-Source-V1.0/Papilio/papilio_pro_lx9_vanilla_ise/ inflating: ZPUino-HDL-Source-V1.0/Papilio/papilio_pro_lx9_vanilla_ise/papilio_pro_lx9_vanilla_ise.xise inflating: ZPUino-HDL-Source-V1.0/zpu/hdl/zpuino/bootloader/bootloader.hex .. file #621 (ZPUino-HDL-Source-V1.0/zpu/hdl/zpuino/bootloader/crt0.S): mismatch between local and central GPF bit 11 ("UTF-8"), continuing with central flag (IsUTF8 = 1) file #662 (ZPUino-HDL-Source-V1.0/zpu/hdl/zpuino/contrib/zpuino_pokey.vhd): mismatch between local and central GPF bit 11 ("UTF-8"), continuing with central flag (IsUTF8 = 1) Perhaps somebody can gide me to a github version of the code? The original author also added some new cool stuff in the 2.0 version
  19. Papilio Pro Beginner Tips

    Hello Jack, Nice to get some feedback. on the subject of the loader I started by downloading ( sha1sum 565f278f7190b04eb7612cd2cdf998119b687070 ) As I just did from the zip contains the following: keesj@700z:~/Downloads/tmp$ unzip ../ Archive: ../ inflating: papilio-loader/license.txt inflating: papilio-loader/papilio-loader.exe inflating: papilio-loader/papilio-loader.jar inflating: papilio-loader/readme.txt inflating: papilio-loader/help/index.htm inflating: papilio-loader/help/images/expert-mode-screen.png inflating: papilio-loader/help/images/installer-preferences-screen.png inflating: papilio-loader/help/images/papilioRed.css inflating: papilio-loader/help/images/simple-mode-screen.png inflating: papilio-loader/images/loader_about.png inflating: papilio-loader/images/right_arrow.png inflating: papilio-loader/programmer/bscan_spi_xc3s100e.bit inflating: papilio-loader/programmer/bscan_spi_xc3s250e.bit inflating: papilio-loader/programmer/bscan_spi_xc3s500e.bit inflating: papilio-loader/programmer/bscan_spi_xc6slx4.bit inflating: papilio-loader/programmer/bscan_spi_xc6slx9.bit inflating: papilio-loader/programmer/linux32/data2mem inflating: papilio-loader/programmer/linux32/devlist.txt inflating: papilio-loader/programmer/linux32/papilio-prog inflating: papilio-loader/programmer/linux32/srec_cat inflating: papilio-loader/programmer/win32/data2mem.exe inflating: papilio-loader/programmer/win32/devlist.txt inflating: papilio-loader/programmer/win32/papilio-prog.exe inflating: papilio-loader/programmer/win32/srec_cat.exe inflating: papilio-loader/ inflating: papilio-loader/papilio_48.png After a chmod +x I still can not execute the shell file keesj@700z:~/Downloads/tmp/papilio-loader$ ./ -bash: ./ /bin/sh^M: bad interpreter: No such file or directory This is probably because the file is encoded using a dos formatting keesj@700z:~/Downloads/tmp/papilio-loader$ dos2unix dos2unix: converting file to Unix format ... Now the loader start working (but I don't give/want and need to give this program root access keesj@700z:~/Downloads/tmp/papilio-loader$ ./ [sudo] password for keesj: hence I start looking at the script(removed the sudo) next I start the script and have the next problem the jar file is expected somewhere. Error: Unable to access jarfile /opt/GadgetFactory/papilio-loader/papilio-loader.jar I give up on the script and start looking at the binaries(found papilio-prog in papilio-loader/programmer/linux32) the programmer ./papilio-prog is lacking ./papilio-prog: error while loading shared libraries: cannot open shared object file: No such file or directory and installing a 32 bits version of that is getting challenging on my system(ubuntu) Worse for me is 32 the bits programmer keesj@700z:~/Downloads/tmp/papilio-loader/programmer/linux32$ file papilio-prog papilio-prog: ELF 32-bit LSB executable, Intel 80386, version 1 (SYSV), dynamically linked, interpreter /lib/, for GNU/Linux 2.6.24, BuildID[sha1]=c9377304b85ce73f71204787840ec0d71880d452, not stripped This is where I started downloading the code from github and found (the source code there doesn't compile on my ubuntu install without some modifications (changed posted on pastebin)) By missing bit code and such I was referring the code found there. has but lack the constrains file and other things like archives of the LogicAnalyer bit files (lacking the lx9) so this is why I ended up there (there are a few more similar problems like ./linbin/diago missing the ncurses library. I will follow the tutorials you mentioned but still would like that the wiki pages I mentioned to get updated as it was not hard for me to find them! And I am looking forward to finding the SUMP VHDL code for the papilio pro!
  20. Papilio Pro Beginner Tips

    Hi, It is now December 2016 and I bought the papilio-pro about a month ago after reading the spartan introduction book and learning about the zpuino . I previously owned a Basys2 board and wanted something new. I bought the logic analyzer set with the papilio pro board and expected (after looking at the video's and such) that it would be a smooth experience to get this stuff running. by now I did gt some basic sample running (e.g. blinking a led) but it was quite a struggle. -papilio-prog binary for linux where outdated (e.g. targetting 32 bits platform) -papilio-prog source code was not compiling -bitfiles to program the pro flash where missing and the VHDL source code was incomplete -There where(are) no ready make bitfiles to turn the pro into a logic analyzer -There is no official place to download the modified source for the SUMP logic analyzer and download have been broken/ don't work -In the last 15 days nobody cared to answer anything on IRC Can somebody/gadgetfactory help me get the basic VHDL SUMP source so we can make a fully working system again? I would like to be able to publish a full set of source code on something like github for people to get a better experience. I am also considering spending some time on making it possible to flash openocd(or urjtag) to program the board as that code is more actively maintained. More notes from IRC bellow: 08:50 < keesj> Hi 08:51 < keesj> I recantly bought a papillio pro and now taking the time to get started with that board 08:52 < keesj> I have some previous experience with VHDL/fpga (reading the intro book) and running samlples on a Basys2 board 08:54 < keesj> I have bought the logic analyze kit with a pro board and want to gets things running (using linux) but I amexperiencing some hurdles to take to do that 08:54 < keesj> the download of the flasher only contained a 32 bits version hence I had to download the souce code and make small modifications (just to make it compile again) 08:55 < keesj> 08:56 < keesj> this was the error log and this my current patch "to make it compile" 08:56 < keesj> unteted yet. Now I am trying to get started reading 08:57 < keesj> but I can not download the bit files (I get a timeout) nor can I download the source 08:58 < keesj> the link to the java client is broken Java Client - Download the latest client from Jawi's Alternate Client Homepage 08:59 < keesj> and there is a smal typo on the page (the text reads twice " Ready to run bitstream for the Papilio One 500K board. Version 2.12, use Papilio Loader to load the bitstream. ") While the second time it shoud be about the 250K version) 09:03 < keesj> it looks like the bitstream can also be found in the git repo under Helper_App/bitstream_archive 09:19 < keesj> I also had to create a udev rule to allow writing to the board as normal user 09:40 < keesj> Next I am haveing a problem wit the programming/programming 09:40 < keesj> Device failed to configure, INSTRUCTION_CAPTURE is 0x19 09:42 < keesj> with an other files worked 09:47 < keesj> I was wondering. what transfer speed can I expect for the logic analyzer ? it it somewhere near usb 2.0 speed e.g. 24 MB/s? 11:02 < keesj> the link on for the SDRAM is broken 14:33 < keesj> Hmm from the looks of it I need to compile a version for the XC6SLX9 myself. 14:34 < keesj> Kinda weird given I have bought the pro with the logic wings in a Logic anaylzer package 15:10 < keesj> some work was already done here 15:18 < keesj> the forum pages do no longer contain the source code 15:19 < keesj> going down the rabbit hole here 22:27 < keesj> I guess I am a little later to the party 22:27 < keesj> also looks good but again missing links 22:29 < keesj> is zo cool