Laurence

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About Laurence

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  1. Thanks guys for your suggestions. The particular problem I had seemed to be caused by clocking a counter from a logic gate fed from outputs of another counter, i.e. to create a particular division ratio. It worked okay until I modified a different part of the design. I suspect that the width of the clock pulse was marginal and so it stopped working when the FPGA was re-routed. I fixed it by clocking the counter directly from another counter output, i.e. a longer pulse. I am not making flip-flops from gates. Agreed, I am sure it is not a good idea to drive clock inputs from combinational logic. I have noticed that ISE warns about this when doing the synthesis. I can see that driving the counter clocks from the system clock would get around this. This then drives us down the synchronous design route. I have not done a lot of real digital design in the past 20 years so I agree that I am a bit out of touch with the design methods used in programmable logic. There is plenty to learn! Thanks again for all of your advice.
  2. Hi. I am new to FPGA design (but an experienced electronics engineer). I am learning how to create simple designs on a Papilio One 500k with ISE schematics. I am familier with basic logic design, and so far I have created some simple combinational logic and a divider chain to produce a 10Hz clock. This works fine, but when after editing and add more bits on, the existing parts no longer function properly. The frustrating thing is that the schematics look correct, but they do not function as expected on the FPGA. After searcing the internet for answers, I suspect it might be something to do with net names or constraints, but that's as far as I have got. Can anyone point me in the right direction (I cannot be the only beginner have these problems!)? By the way, I am aware there are limitations in using schematics (compared with using Verilog or VHDL). I am developing this project for my college students and there will be insufficient time for them to learn an HDL, although I will of course give them an introduction to the subject. Many thanks for reading this.
  3. Does DesignLab rely on (superseded) ISE?

    Thank you offroad and Jack for your help. I have a much clearer understanding now. My conclusion is: ISE is still usable, but not compatible with the newest devices. Vivado is not a real option as it does not easily run on Windows 10 (and does not offer schematic input). Papilio with Designlab is a good option for introducing FPGAs. For teaching FPGA programming, Verilog or VHDL is a must as this is how FPGAs are developed in industry. It looks like Papilio and Designlab are the way to go for my current students. The syllabus is quite old, so will need to include logic design using old-school logic devices, e.g. 74HC series. As soon as possible I will move them onto programmable logic with them implementing simple designs on FPGAs, initially using schematics. They can analyse the code produced from simple logic circuits, but there would be no need for them to learn VHDL or Verilog at this stage. Jack - I may contact you outside of the forum regarding your offer. Laurence
  4. Hi, I am new to this forum. I am running a course on logic design and I want to include a practical introduction to FPGAs. I am considering Papilio as the platform to use as there will not be time to learn VHDL or Verilog. My students are already used to using schematic design tools such as Proteus. We are using Windows 10. Is Papilio the right solution? I understand that Xilinx have superseded ISE with Vivado (which is more complicated and does not allow schematic entry). How does this affect Papilio and DesignLab? Many thanks.