GadgetFreak

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About GadgetFreak

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  1. just given that WB version a quick try but it fails on finding the device, so went back to the standard duo bit file and sampled at 20Mhz. It didn't look any better, so removed the clip probes and went with the jumper wires and the results look better but I still seem to get issues where some lines give a square wave when they are permanently high. I need to make some time to play and test properly, at the moment I have too many projects on the go and no time for anything really. Also once my spare wing arrives from the USA I can see if that fixes the problem. Thanks for all your help so far and I will keep you posted on my progress.
  2. Good suggestions but the cable connection was just moved from one board to the other so all 8 channels were connected and so was the ground and of course all using the same wires to rule a broken wire out. Not sure about the voltage threshold. Is there an option for this on the DUO? I am wondering if I have a bad LA wing ?
  3. Hello again, I now have another LA, its only 8 channels and is an addon for my Scope board. I have probed the same connections with both, although on the Duo the channels are reversed as I used the same probe cables so as to rule these out of the issue. As you can see from the following 2 pictures the Duo LA seems to generate square waves even when the signal remains high, why is this?
  4. Thanks for the replies I am trying to pin down what is going wrong with an emulated chip compared to the original one. The chip basically switches the 2 upper address lines of an eprom under special circumstances. In a dedicated test board it works fine but in the real board it is failing. Originally I was monitoring all 14 address lines and the Output Enable. I was setting triggers to occur on certain memory locations and it seemed to trigger correctly but the data displayed did not match the trigger conditions. So I then tried to simplify it by just monitoring the 2 upper address lines and the Enable. The trouble is without all the address lines I need to capture a much longer data stream, around 500ms, so that I have enough data to compare the whole boot sequence. I have been coding since the early 80's, both low level & high level, on embedded micros upto minis, but this is my first time playing with an LA. Scopes and logic are no issue normally for me but so far with this board and software I am not getting what I expected to see. Perhaps I should set it all up again with the full set of address lines and take some screen grabs to show you what I am seeing... Of course a secondary reason for purchase is to start VHDL coding, its that 'little' something that has been missing from my life
  5. Am pretty certain I do need an external clock as I am looking at chip select and address lines on a PCB using a 68000 CPU at 8Mhz. The only way to cleanly see the line states is to match the clock speed as this is when the transitions occur and by clocking at the CPU speed I can get more capture time. Running at 10Mhz reduces my capture time. There is an issue somewhere with the external clock mode though in that the capture time should be a factor of the external clock whereas in the current code it changes with the 'unused' capture frequency that was selected when the Internal mode was last selected. The other thing I have noticed is that the RLE mode appears to be bugged. Firstly, I get lots of noise on unused channels in a group, even when I ground them out. And secondly I seem to get square waves whenever a signal goes high and stays high. I have checked this with a scope to verify the line is just high and not pulsing! So far I am not having much success.... I keep hoping I will find something that I am doing wrong.... but so far no such luck. There is a switch on the Duo just at the end of the board near the C/D wing connectors. What does it do? Also I presume when using a single LA wing it goes away from the Duo, hanging off the board so to speak?
  6. I have played a bit more and it seems that the capture window size still changes depending on the underlying Internal Clock. I proved this by changing back to internal clock and reducing the frequency then switching back to an External clock and noting the Capture Window time. I am taking the clock from an 8Mhz 68000 CPU and once I slowed down the capture rate to 10Mhz I noted that I do get some variation in the rom enable line but it still does not seem to be working with the triggers correctly or I am getting incorrect data displayed.
  7. Took me a while to find the syntax for the cfg file, "INTERNAL, EXTERNAL_RISING, EXTERNAL_FALLING" It seems to be working but I am not 100% sure as I don't seem to be getting the correct data displayed. In that I set a Simple Trigger Mask of 0x4000 and a Value of 0x0000 as channel 14 is connected to a rom enable line which is active low. It does seem to trigger at the correct time in that it will wait longer if I start the capture several seconds before I know the rom is being accessed. But the displayed data always seems to show channel 14 as high for the whole dump, even at the 0.0us line. Is it something I am missing about the triggers?
  8. Hi, I have been testing out the Duo with the Logic Analyzer loaded from the DesignLab. When configuring there is a dropbox for Sampling Clock but it will not let me select anything other than internal. I need to use an external clock.... Is this not possible with the Duo or do I need to load a different bit file.