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About virtualrobotix

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  1. If you want to discuss live about the specification and requirment of an APM system my skype account is : virtualrobotix best Roberto
  2. Hi Jack , I'm happy that you like this idea ... I already developed an Autopilot : VR Brain 5 that is the first board that support 32 bit processor i use STM32F4 . So i investigate some about the power of ZPuino it's similar to AVR x 6 ... Actually STM32F4 is like AVR x 22 the main difference is that on STM32F4 there is a math co processor. So for develop a good autopilot we need 2-3 serial port 1 or 2 SPI BUS 1 i2C BUS . Actually we use as sensor MPU6500 (SPI) , MSIC Barometer (SPI ) HMC5883 (i2C) GPS ( 1 Serial Port ) Telm1 and Telm2 (serial Port) As dev tool we use Eclipse the 32 bit version of code is near 700 kbyte on flash the 8 bit version is 250 kbyte . ATMEGA 2560 . The actual version of Ardupilot have a Hardware Abstraction Layer where is implemented the driver for interface the hardware in low level with OS or without OS . So the main work could be write the HAL interface for ZPUINO without OS ... Actually we use on STM32F4 nuttx os . Why develop on FPGA with a softcore ? Because it's cool And so we could have a indipendent hard core cpu autopilot ... We intend to investigate also about the use of zinq or other fpga for : IQ RF Modulator , Video Stabilization , DVB-T modulator , Stereo Camera , H264/5 compressor and a lot of cool functionality for robotic application This is our repo : I don't have so much experience on VHDL programming and don't know the limit of FPGA so what do you think about the different option that i explain in my post ?
  3. Thank you Jack for your support And congratulation for your great Job on FPGA . I discover a new world and learn a lot on FPGA by your great opensource project. I'm co founder of another great opensource project. ... I'm evaluate how we can integrate this 2 worlds. I think could be possible or with softcore cpu , sdr or camera .... Mumble Mumble Mumble What do you think about ? More simple task could be port ardupilot on softcore like avr 8 or zpuino . Best Roberto
  4. Thanks Jaxartes for your reply . I recived a mail from developer of code and he told me that not need use all the signal in the bus but only someone now i try to understand better who are need and what i don't need to try to integrate in my papilo board sure could be possible to implement different tutorial or modify code already available for understand better how work the bus. Do you have a link to some tutorial ? What i don't need exactly is how is connected the bus to module in the code ... so if i think to the schematics is clear how connect some pin to other ... but in the bus is not wire connected to other divice but buy a bus so i don't exactly understand how connect specific pin to other specific pin in the module that is not clear to me but try to learn myself or with some support for the community But when the bus is connected in ZPuino how i see that bus by a mechanism like ioclt or memory access to a specific memory location is correct ? bye and thanks a lot Roberto
  5. I found an interesting project it is advanced implementation in OpenCores of FM Trasmitter that accept in input an audio streaming and add it to FM RF modulation . The project is this : FM Transmitter Hack,wbfmtx This is the link to the code :,filedetails?repname=wbfmtx&path=%2Fwbfmtx%2Ftrunk%2Frtl%2Fwbfmtxhack.v What i understand is that module is in verilog and not in vhdl is possible to develop a project with mixed language ? This is my first question . The other question is about wishbone bus , i read the implementation in ZPUINO I follow this tutorial it's clear but i have some problem to understand how the wishbone bus describe in ZPuino is compatibile with the module that i would add to my project. -- -- IO SLOT 9 -- slot9: zpuino_empty_device port map ( wb_clk_i => wb_clk_i, -- Clock to peripheral. wb_rst_i => wb_rst_i, -- Reset to peripheral. wb_dat_o => slot_read(9), -- Data from peripheral. wb_dat_i => slot_write(9), -- Data to peripheral. wb_adr_i => slot_address(9), -- Address to peripheral. wb_we_i => slot_we(9), -- Write-enable to peripheral. wb_cyc_i => slot_cyc(9), -- Cycle handshake to peripheral. wb_stb_i => slot_stb(9), -- Chip-select to peripheral. wb_ack_o => slot_ack(9), -- handshake acknowledge from peripheral. wb_inta_o => slot_interrupt(9), -- Interrupt from peripheral. id => slot_ids(9) -- Peripheral ID (not part of Wishbone). ); And the interface inside the module , but my opinion is it is different or i don't understand how interface the bus ? I have experience in schematics design of micro controller and memory bus so i understand the bus concept but i don't understand how the ZPuino bus could be compatible with wbfmtxhack this is the whisbone descriprtion : It's different respect the bus in ZPuino i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, o_wb_ack, o_wb_stall, o_wb_data, What i don't understand ? I'm a very good background in C / C++ but is the first time that i try to develop a complex code on FPGA . Someone can help me please to understand please Best Roberto
  6. In my previous test i already done this step but the result of new IP was quite different respect simple dcm in the description ... but after read the course i confident about apply right change to the code for my great PAPILIO DUO board
  7. Hi offroad , thanks for your reply ... today i try other sample that i found around the network ... With this code i change the name of variable with the description that i found in papilio_duo ucf file ... I don't know exactly if is possible assign a variable like arduino_0 port to another name like LED0 . Is possible to mantain the same .ucf and assign the LED0 <= Arudino_0 or is a wrong syntax or is possilbe ? The variable assigned at phisical pin are global in VHDL code ? or is as in 'c' languange that exist local and global variable ? I used that definition in the .udf for assign Phisical pin in right position : NET CLK LOC="P94" | IOSTANDARD=LVTTL; # CLK TIMESPEC TS_Period_1 = PERIOD "CLK" 31.25 ns HIGH 50%; NET TXD LOC="P141" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # TX NET RXD LOC="P46" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # RX NET Arduino_0 LOC="P116" | IOSTANDARD=LVTTL; # A0 NET Arduino_1 LOC="P117" | IOSTANDARD=LVTTL; # A1 NET Arduino_2 LOC="P118" | IOSTANDARD=LVTTL; # A2 I compiled the code and obtain morse.bit file so i think that i did a step forward .. and i'm ready to test the program to FPGA Now the only doubt is about the frequency set on trasmitter with actual clock setting. For change the periood i think that i to change the TIMESPEC definition .. to value that corrispond to frequency that i would use for my modulator is correct ? Best Roberto
  8. Hi offroard, thanks very much for your reply ... and link to course . I'm a new with VHDL so i have some limit and need study The main problem that i was is on DCM IP that is not available for Spartan 6 and so cannot follow the tutorial now try how i can write a work around. Best Roberto .
  9. Dear Friends, i'm very happy to Papilio DUO board. I try the SDK software on windows 10 but don't work , with Linux ubuntu instead all work fine. So now i try ISE and compile this code : I have some problem during compiling i have this error : ERROR:NgdBuild:604 - logical block 'fast_clock' with type 'clocking' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'clocking' is not supported in target 'spartan6'. Can you help me to understand how solve the problem ? I try to found DCM with Spartan6 it isn't supported. So i don't know how solve the iusse on the code . best Roberto Navoni