prismprojection

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  1. I need help tracing down a warning and general improvements. Here is the warning: Signal <max_counter> is used but never assigned. This sourceless signal will be automatically connected to value 11111111111111111111 Here the VHDL code for a 20-bit PWM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity Generic_PWM_x1 is port( clk: in std_logic; pwm_var: in std_logic_vector(19 downto 0); pwm_out: out std_logic ); end Generic_PWM_x1; architecture Behavioral of Generic_PWM_x1 is signal counter: std_logic_vector(19 downto 0):= (others=>'0'); signal max_counter: std_logic_vector(19 downto 0):= (others=>'1'); begin process(clk) begin if rising_edge(clk) then counter <= std_logic_vector( unsigned(counter) + 1 ); if counter=max_counter then counter<=(others=>'0'); else if counter<pwm_var then pwm_out<='1'; else pwm_out<='0'; end if; end if; end if; end process; end Behavioral; It seems to me that it's assigned, so I need some guidance. In general, I'm also interested in improving the timing of this block, so any suggestions would be very much appreciated. Thanks!
  2. Hi Jack, No worries. I'll take a rain-check on answering more questions =) I ordered the Papilio One 500K and LogicStart MegaWing today, and I'm very excited to start learning on actual hardware. Thanks, Garrett
  3. Nevermind, I figured it out.
  4. I changed it to " Papilio_Default_Wing_Pinout" which removed the previously mentioned errors ... now the Mapping process clears all the logic. Is it that nothing is really connected to the IO pins? I thought adding the hardware symbol would allow access to the GPIO. There isn't a soft core processor in this design.
  5. The schematic has been corrected and simulated. The next hurdle is I added "Papilio_Default_Pinout.vhd" to gain access to the boards GPIO for the PWM value and output, but I receive the following errors when I try to implement the top module. ERROR:HDLParsers:3317 - "C:/DesignLab-1.0.7/libraries/Papilio_Hardware/Papilio_Default_Pinout.vhd" Line 23. Library board cannot be found. ERROR:HDLParsers:3013 - "C:/DesignLab-1.0.7/libraries/Papilio_Hardware/Papilio_Default_Pinout.vhd" Line 24. Library board is not declared. Process "Synthesize - XST" failed What can I do to resolve this? Thanks.
  6. I need a 20-bit PWM with the counter clocked at 210MHz or greater. I looked at the RCL_PWM_x48 symbol code and tried to modify it to accept a clock separate from the soft core. Can someone take a look at the following and let me know if I'm on the right track? Thanks! -------------------------------------------------------------------------------- -- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 14.7 -- \ \ Application : -- / / Filename : xil_12112_30 -- /___/ /\ Timestamp : 09/23/2014 15:24:59 -- \ \ / \ -- \___\/\___\ -- --Command: --Design Name: -- library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; --library work; --use work.Wishbone_to_Registers_n_package.all; library DesignLab; use DesignLab.ALL; use DesignLab.Wishbone_to_Registers_n_package.all; entity PWM_20b_x5 is generic ( pwm_count : integer := 5; pwm_width : integer := 20; register_count : integer := 5 --Each PWM has 1 register ); port ( wishbone_in : in std_logic_vector (100 downto 0); wishbone_out : out std_logic_vector (100 downto 0); --Put your external connections here PWM : out std_logic_vector(pwm_count-1 downto 0) -- DIR : out std_logic_vector(pwm_count-1 downto 0); PWM_clk : in std_logic ); end PWM_20b_x5; architecture BEHAVIORAL of PWM_20b_x5 is COMPONENT Wishbone_to_Registers_n generic ( register_count : integer := register_count ); PORT( wishbone_in : IN std_logic_vector(100 downto 0); wishbone_out : OUT std_logic_vector(100 downto 0); PWM_clk : in std_logic; register_in : in register_type(0 to register_count-1); register_out : out register_type(0 to register_count-1) ); END COMPONENT; COMPONENT PWMGenerator generic ( C_PWM_WIDTH : integer := pwm_width; C_PWM_TYPE : integer := 1 -- 2 phase, 1 phase or Enable chopping ); PORT( Clk : in std_logic; Duty : in std_logic_vector(C_PWM_WIDTH-1 downto 0); Out1 : out std_logic; Out2 : out std_logic ); END COMPONENT; signal register_in_array : register_type(0 to register_count-1); signal register_out_array : register_type(0 to register_count-1); signal DIR : std_logic_vector(pwm_count-1 downto 0); signal PWM_clk : std_logic; --Put your unique register names here begin --Put your code here GEN_PWMS: for j in 0 to pwm_count-1 generate Inst_pwm_inst: PWMGenerator GENERIC MAP( C_PWM_WIDTH => pwm_width, C_PWM_TYPE => 1 ) PORT MAP( CLK => PWM_clk, Duty => register_out_array(j)(pwm_width-1 downto 0), Out1 => PWM(j), Out2 => DIR(j) ); --register_in_array(j) <= register_out_array(j); --So we can read back what was written to the register. end generate GEN_PWMS; --Do not touch Inst_Wishbone_to_Registers_n: Wishbone_to_Registers_n generic map (register_count => register_count) PORT MAP( wishbone_in => wishbone_in, wishbone_out => wishbone_out, clk_96Mhz => clk_96Mhz, register_in => register_in_array, register_out => register_out_array ); end BEHAVIORAL;
  7. Ok, I figured out a work around. You can force a clock on a signal net. (http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/ism_db_clock.htm) Next problem ... The PWM isn't working correctly.
  8. So, I'm still struggling with this. I added this source file to the simulation, but I'm unclear how to connect "clk_200" to my schematic. (I removed the clk_32to288_dcm symbol and renamed the net to clk_200, but I guess ISE doesn't know they are connected) -- TestBench Template LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; entity tb is end entity; architecture sim of tb is -- Procedure for clock generation procedure clk_gen(signal clk : out std_logic; constant FREQ : real) is constant PERIOD : time := 1 sec / FREQ; -- Full period constant HIGH_TIME : time := PERIOD / 2; -- High time constant LOW_TIME : time := PERIOD - HIGH_TIME; -- Low time; always >= HIGH_TIME begin -- Check the arguments assert (HIGH_TIME /= 0 fs) report "clk_plain: High time is zero; time resolution to large for frequency" severity FAILURE; -- Generate a clock cycle loop clk <= '1'; wait for HIGH_TIME; clk <= '0'; wait for LOW_TIME; end loop; end procedure; -- Clock frequency and signal signal clk_200 : std_logic; begin -- Clock generation with concurrent procedure call clk_gen(clk_200, 200.000E6); -- 200.000 MHz clock -- Time resolution show assert FALSE report "Time resolution: " & time'image(time'succ(0 fs)) severity NOTE; end architecture;
  9. Can I gain access to the 32Mhz clock without using the ZPUino core? I added the "CLK" net marker from the utility schematic, but when I try to simulate the circuit in ISE the "CLK" line isn't oscillating. I've attached my schematic. I'm trying to make a 20-bit PWM. Ultimately the constant value will be from GPIO pins. Thanks.