leon912

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  1. Hi Alvie, thanks for your reply. 1. I used the Hamster's SDRAM model to run simulation on modelsim but the model itself doesn't work. For this reason I tested my component directly on the papilio board and it happened that, after writing x"41424344", the output was x"43444142", so the 2 16-bit words were swapped; for this reason I changed the code of the controller swapping the values "data_out <= captured_data_last & captured_data;". 2. I checked my code and I don't see how I write twice in the same address: I have a counter that after each write increases the address so the write is done only once in each different address. 3. I wait for the cmd_ready to be 1 only because it was suggested to me to do so. 4. Regarding the reads, I do read twice from the same address for the following reason: as I wrote in the past posts, when I write for example ABCD EFGH IJKL MNOP and I try to read from the same memory location in the same order, I read: MNCD ABGH EFKL IJOP so it seems like that the first 16-bit word keeps the old value; reading the first time, discarding the data and the reading again from the same location, was the best solution. As I said, I tryied this code of the papilio board, not only in simulation with modelsim or GTKWAVE, and it works. Maybe you got a different code for the model or the controller with respects to me. Have you tryied to implement everything on the board?
  2. Hi, the only thing I can give you is the FSM I wrote to read/write from the memory through the memory controller. At the output of the memory controller I have a register to sample the read value and this register is enabled by sdram_data_ready generated by the controller itself. Finally the output of the register (which is a 32 bit word) is divided in 4 bytes and sent to a mux4x1 that selects the byte to be sent via usb. library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all; entity FSM_SDRAM_TO_UART isport( rst : in std_logic;clk : in std_logic;led : out std_logic;-- SDRAM CONTROLLER signalscmd_ready : in STD_LOGIC; -- '1' when a new command will be acted on cmd_enable : out STD_LOGIC; -- Set to '1' to issue new command (only acted on when cmd_ready = '1') cmd_wr : out STD_LOGIC; -- Is this a write? cmd_address : out STD_LOGIC_VECTOR(20 downto 0); -- address to read/write cmd_byte_enable : out STD_LOGIC_VECTOR(3 downto 0); -- byte masks for the write command cmd_data_in : out STD_LOGIC_VECTOR(31 downto 0); -- data for the write command sdram_data_ready : in std_logic; mux_ctrl : out std_logic_vector(1 downto 0); -- UART CONTROLLER signals uart_new_data : out std_logic; uart_busy : in std_logic); -- signs that transmitter is busyend entity FSM_SDRAM_TO_UART; architecture BEHAVIOURAL of FSM_SDRAM_TO_UART is type state_type is ( IDLE, WRITE0, INCR_ADDR0, WAIT0, WRITE1, INCR_ADDR1, WAIT1, WRITE2, INCR_ADDR2, WAIT2, WRITE3, INCR_ADDR3, WAIT3,READ_TEST, WAIT_TEST, READ0, SAMPLE, SAMPLING, SEND_UART0, WAIT_UART0, SEND_UART1, WAIT_UART1, SEND_UART2, WAIT_UART2, SEND_UART3, INCR_ADDR, WAIT_READ, STOP); signal CURRENT_STATE, NEXT_STATE : state_type; signal sdram_addr : STD_LOGIC_VECTOR(20 downto 0);signal addr_incr : std_logic;signal addr_rst : std_logic; begin cmd_address <= sdram_addr; FSM_REG : process (clk, rst) begin if rst = '1' then CURRENT_STATE <= IDLE; elsif (clk'event and clk = '1') then CURRENT_STATE <= NEXT_STATE; end if; end process FSM_REG; process(clk, rst, addr_incr, addr_rst)variable temp : integer := 0; begin if(rst = '1' OR addr_rst = '1') then temp := 0; elsif(clk'event AND clk = '1') then if(addr_incr = '1') then if(temp = 5) thentemp := 0;elsetemp := temp + 1;end if;end if;end if; sdram_addr <= std_logic_vector(to_unsigned(temp, sdram_addr'length));end process; FSM_OUT : process (CURRENT_STATE) begin case CURRENT_STATE is when IDLE =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '0';addr_rst <= '1';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '0'; led <= '0';mux_ctrl <= "00"; when WRITE0 =>cmd_enable <= '1';cmd_wr <= '1';addr_incr <= '0';addr_rst <= '0';cmd_byte_enable <= "1111";cmd_data_in <= x"41424344";uart_new_data <= '0'; led <= '0';mux_ctrl <= "00"; when INCR_ADDR0 =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '1';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '0'; led <= '0';mux_ctrl <= "00"; when WAIT0 =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '0';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '0'; led <= '0';mux_ctrl <= "00"; when WRITE1 =>cmd_enable <= '1';cmd_wr <= '1';addr_incr <= '0';addr_rst <= '0';cmd_byte_enable <= "1111";cmd_data_in <= x"45464748";uart_new_data <= '0'; led <= '0';mux_ctrl <= "00"; when INCR_ADDR1 =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '1';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '0'; led <= '0';mux_ctrl <= "00"; when WAIT1 =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '0';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '0'; led <= '0';mux_ctrl <= "00"; when WRITE2 =>cmd_enable <= '1';cmd_wr <= '1';addr_incr <= '0';addr_rst <= '0';cmd_byte_enable <= "1111";cmd_data_in <= x"494A4B4C";uart_new_data <= '0'; led <= '0';mux_ctrl <= "00"; when INCR_ADDR2 =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '1';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '0'; led <= '0';mux_ctrl <= "00"; when WAIT2 =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '0';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '0'; led <= '0';mux_ctrl <= "00"; when WRITE3 =>cmd_enable <= '1';cmd_wr <= '1';addr_incr <= '0';addr_rst <= '0';cmd_byte_enable <= "1111";cmd_data_in <= x"4D4E4F50";uart_new_data <= '0'; led <= '0';mux_ctrl <= "00"; when INCR_ADDR3 =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '1';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '0'; led <= '0';mux_ctrl <= "00"; when WAIT3 =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '0';addr_rst <= '1';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '0'; led <= '0';mux_ctrl <= "00"; when READ_TEST =>cmd_enable <= '1';cmd_wr <= '0';addr_incr <= '0';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '0'; led <= '0'; mux_ctrl <= "00"; when WAIT_TEST =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '0';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '0'; led <= '0'; mux_ctrl <= "00"; when READ0 =>cmd_enable <= '1';cmd_wr <= '0';addr_incr <= '0';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '0'; led <= '0'; mux_ctrl <= "00"; when SAMPLE =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '0';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '0'; led <= '0';mux_ctrl <= "00"; when SAMPLING =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '0';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '0'; led <= '0';mux_ctrl <= "00"; when SEND_UART0 =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '0';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '1'; led <= '0';mux_ctrl <= "00"; when WAIT_UART0 =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '0';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '0'; led <= '0';mux_ctrl <= "01"; when SEND_UART1 =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '0';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '1'; led <= '0'; mux_ctrl <= "01"; when WAIT_UART1 =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '0';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '0'; led <= '0';mux_ctrl <= "10"; when SEND_UART2 =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '0';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '1'; led <= '0';mux_ctrl <= "10"; when WAIT_UART2 =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '0';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '0'; led <= '0';mux_ctrl <= "11"; when SEND_UART3 =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '0';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '1'; led <= '0';mux_ctrl <= "11"; when INCR_ADDR =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '1';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '0'; led <= '0';mux_ctrl <= "00"; when WAIT_READ =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '0';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '0'; led <= '0';mux_ctrl <= "00"; when STOP =>cmd_enable <= '0';cmd_wr <= '0';addr_incr <= '0';addr_rst <= '0';cmd_byte_enable <= "0000";cmd_data_in <= x"00000000";uart_new_data <= '0'; led <= '1';mux_ctrl <= "00"; end case; end process; FSM_NEXT_STATE : process(CURRENT_STATE, uart_busy, cmd_ready, sdram_data_ready, sdram_addr)begincase CURRENT_STATE iswhen IDLE => if (cmd_ready = '1') thenNEXT_STATE <= WRITE0;elseNEXT_STATE <= IDLE;end if; when WRITE0 => if (cmd_ready = '0') thenNEXT_STATE <= INCR_ADDR0;elseNEXT_STATE <= WRITE0;end if; when INCR_ADDR0 => NEXT_STATE <= WAIT0; when WAIT0 => if (cmd_ready = '1') thenNEXT_STATE <= WRITE1;elseNEXT_STATE <= WAIT0;end if; when WRITE1 => if (cmd_ready = '0') thenNEXT_STATE <= INCR_ADDR1;elseNEXT_STATE <= WRITE1;end if; when INCR_ADDR1 => NEXT_STATE <= WAIT1; when WAIT1 => if (cmd_ready = '1') thenNEXT_STATE <= WRITE2;elseNEXT_STATE <= WAIT1;end if; when WRITE2 => if (cmd_ready = '0') thenNEXT_STATE <= INCR_ADDR2;elseNEXT_STATE <= WRITE2;end if; when INCR_ADDR2 => NEXT_STATE <= WAIT2; when WAIT2 => if (cmd_ready = '1') thenNEXT_STATE <= WRITE3;elseNEXT_STATE <= WAIT2;end if; when WRITE3 => if (cmd_ready = '0') thenNEXT_STATE <= INCR_ADDR3;elseNEXT_STATE <= WRITE3;end if; when INCR_ADDR3 =>NEXT_STATE <= WAIT3; when WAIT3 => if (cmd_ready = '1') thenNEXT_STATE <= READ_TEST;elseNEXT_STATE <= WAIT3;end if; when READ_TEST => if (cmd_ready = '0') thenNEXT_STATE <= WAIT_TEST;elseNEXT_STATE <= READ_TEST;end if; when WAIT_TEST => if (cmd_ready = '1') thenNEXT_STATE <= READ0;elseNEXT_STATE <= WAIT_TEST;end if; when READ0 => if (cmd_ready = '0') thenNEXT_STATE <= SAMPLE;elseNEXT_STATE <= READ0;end if; when SAMPLE => if (sdram_data_ready = '1') thenNEXT_STATE <= SAMPLING;elseNEXT_STATE <= SAMPLE;end if; when SAMPLING =>NEXT_STATE <= SEND_UART0; when SEND_UART0 => if (uart_busy = '1') thenNEXT_STATE <= WAIT_UART0;elseNEXT_STATE <= SEND_UART0;end if; when WAIT_UART0 => if (uart_busy = '0') thenNEXT_STATE <= SEND_UART1;elseNEXT_STATE <= WAIT_UART0;end if; when SEND_UART1 => if (uart_busy = '1') thenNEXT_STATE <= WAIT_UART1;elseNEXT_STATE <= SEND_UART1;end if; when WAIT_UART1 => if (uart_busy = '0') thenNEXT_STATE <= SEND_UART2;elseNEXT_STATE <= WAIT_UART1;end if; when SEND_UART2 => if (uart_busy = '1') thenNEXT_STATE <= WAIT_UART2;elseNEXT_STATE <= SEND_UART2;end if; when WAIT_UART2 => if (uart_busy = '0') thenNEXT_STATE <= SEND_UART3;elseNEXT_STATE <= WAIT_UART2;end if; when SEND_UART3 => if (uart_busy = '1') thenNEXT_STATE <= INCR_ADDR;elseNEXT_STATE <= SEND_UART3;end if; when INCR_ADDR =>NEXT_STATE <= WAIT_READ; when WAIT_READ =>if (to_integer(unsigned(sdram_addr)) = 4) thenNEXT_STATE <= STOP;elsif (cmd_ready = '1' AND uart_busy = '0') thenNEXT_STATE <= READ_TEST;elseNEXT_STATE <= WAIT_READ;end if; when STOP =>NEXT_STATE <= STOP; when others =>NEXT_STATE <= IDLE; end case;end process; end architecture;
  3. Yes, i'm writing ascii. Doing other tests, I discovered that if i do consecutive writes, there is no problem but when i try to read consecutively, 1 of the 2 16-bit words is stick to the previous value of the i/o bus. To be clearer: I write: ABCD EFGH IJKL MNOP and when I read, I get MNCD ABGH EFKL IJOP The only solution I found was to perform a read, discard the result, read again and keep that one as a good result. In that way it works but the bandwidth is halved. Do you know any usefull solution?
  4. Ok, I got a problem. I'm still testing the SDRAM and I got the following error: I write the following 32-bit words: "DCBA" in addr 54 "HGFE" in addr 1024 "LKJI" in addr 1048576 "PONM" in addr 2097151 When I try to read from addr 54 I get "POBA"; if i read from addr 1024 i get "POFE". So it seems like that the most significant 16-bit word remains stuck at the last writing whereas the least significant 16-bit word is read correctely. I didn't change hamster's code (except for the swap of "captured data" that i mentioned few posts before), so where do u think is the error?
  5. Hi, i write and read a burst without problem! The best way is to put a register at the output of the controller to sample the data_output and using the data_output_ready as a load enable for the register
  6. Hi, tomorrow I will test the controller performing many consecutive writes and then reading what i've written. I'll tell u if i get any error
  7. Hi all, thanks to your suggestions I was able to read and write to/from the sdram. However i found a mistake inside the description of the sdram_controller by hamster: when i write a 32 bit word like x"44434241" which is DCBA and then I read it, i get BADC. Reading Hamster's code i found the possible mistake which is the line : if data_ready_delay(0) = '1' then data_out <= captured_data & captured_data_last; data_out_ready <= '1'; end if; I swapped the two captured data and captured_data_last and I read correctly DCBA. Has anyone encountered this error? Or it's me doing something wrong? Leon
  8. Yes, I was talking about designLab. My sistem should be able to take data from OV7670 camera, store them in to the SDRAM and plot them on the monitor via VGA cable. In addition I need a component that works as a scope and prints on my pc monitor the value of data flowing in whichever bus I choose (I already implemented this component). My question is if designLab can help me doing all this complex system or if it's better to design everything with simple VHDL. Leon
  9. HI, thanks for your answer! I'll follow the path that you said and i'm planning of doing it entirely in VHDL without using any of the tools related with the papilio pro board. Do you think that using one of those can help me in speed up the design/test phase?
  10. Ok perfect! Thanks! One last thing: if i write in the memory and then i want to check that the writes have been execute correctely, is there any vhdl component that allows me to pick up the data and show them, for instance, on the computer monitor using putty (so serial transaction?). I found some vhdl code that implements a serial comunication through the USB but nothing suites me and I have to adapt the code to my architecture and this takes a lot of time. I was wondering if there was a time-saving solution for testing purposes leon
  11. Ok but there is something still not clear: constant sdram_address_width : natural := 22; constant sdram_column_bits : natural := 8; constant sdram_startup_cycles: natural := 10100; -- 100us, plus a little more constant cycles_per_refresh : natural := (64000*100)/4196-1; constant test_width : natural := sdram_address_width-1; -- each 32-bit word is two 16-bit SDRAM addresses this is a piece of code from the top_level entity. I know that the memory has words of 16 bits, so if i need to read/write 32 bits i need to specify 2 addresses, right? In addition I read that each address is composed of 8 bits to specify the column (A0-A7), A8,A9,A11 nothing and A10 to enable/disable precharge; plus there are B0-B1 to specify the bank address. I would like to know if i have to deal with those things of if I have to act like i have a 22bit address memory. Thanks!
  12. Ok thanks! There is any manual or commented code that explains how to use the memory controller (how to enable signals, etc..)?
  13. Regarding the usb communication, is it possible to use the USB host shield of arduino with the papilio pro? Usually the shields work with 5V but the papilio provides only 3.3 V
  14. Thanks! I'll try them and I'll tell if i'm able to do what i want. In that case i'll share all the details! Leon
  15. I read the VHDL code of Hamster but what I do not understant is its physical implementation: as i said, i would like to know why the controller requires a data bus and address bus that are twice the ones required by the memory. Can somebody explain it ?