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Everything posted by bnusbick

  1. SUMP Logic analyzer not responding

    Try making channel 2 always high and see if OLS still stops working. Blake
  2. Wishbone version of the Sump Blaze Logic Analyzer

    Both Jawi's OLS client and the one that comes with Designlab 1.07 and 1.08 seem to have the same problem for me.
  3. Wishbone version of the Sump Blaze Logic Analyzer

    Jack, When I replace the following in result = String.format( "comm:%s;baudrate=%d;bitsperchar=8;parity=none;stopbits=1;flowcontrol=xon_xoff", with: result = String.format( "comm:%s;baudrate=%d;bitsperchar=8;parity=none;stopbits=1;flowcontrol=off", it no longer hangs when I send the test pattern, or when I make channels 0,1, and 4 high on the Papilio One 250K OLS client. Having a logic analyzer hang when it receives 0x13 during data acquistion is very undesirable to me. Blake
  4. Wishbone version of the Sump Blaze Logic Analyzer

    Hi Jack, I was able to debug the OLS application in Eclipse. When it was hanging, the host was receiving all 1024 characters, but was hanging when the host was in the loop sending CMD_RST five times. It was actually hanging the second time it sent the CMD_RST. When I modified the source so it would only send CMD_RST once, it hung on closing the port (it does this after every data acquisition). Since this seemed to be a driver issue below OLS, I went back to trying to figure out why it hangs when I send a certain sequence. I was able to isolate it the value 0x13, which is the flow control character. If I take the Papilio 250 with the standard OLS client and short channels 0, 1, and 4 to 3.3 volts, it hangs the exact same way (I am only using Channel group 0). I would think the solution would be to get both sides to ignore flow control. Do you have any thoughts on how to achieve this? I am running on Linux, so I don't know if it would display the same behavior on Windows. Blake
  5. Wishbone version of the Sump Blaze Logic Analyzer

    Jack, When I use the attached test program, if I modify SendIfReady() so it sends a test pattern, the capture completes successfully if I mask out bit 4, but if I don't mask bit 4 out, the capture doesn't complete until I upload new code, at which point it completes and displays the bit 4 value correctly. It is as if it is hanging draw channel-4. I don't see how the value of the data should affect whether the capture completes. I am pretty sure 1024 bytes is the correct amount to send, since if I send less than that with bit 4 masked, the capture won't complete until I upload new code. What would be required to debug the Java LogicSniffer Client program to see if it is in fact receiving all the data? Is there a way I can monitor the serial line to see if it is actually sending all the data? To get it to hang, just modify the following line: Serial.write(test_val++ & 0xef); to: Serial.write(test_val++ & 0xff); I have configured the Logic Sniffer as follows: Connection: Papilio DUO - Wishbone Memory Acquisition: Sampling Rate 5.000 kHz, Channel Groups 0, Recording size 1.00 kB Blake OLS_Client.ino
  6. Wishbone version of the Sump Blaze Logic Analyzer

    Never mind. Looking at the schematic, I see that only Arduino 0-13 are assigned. When I switch to using 12 and 13, I see the toggles.
  7. Wishbone version of the Sump Blaze Logic Analyzer

    Jack, When I configure Zpuino GPIOs 14 and 15 as output and try to toggle them, I see no output in OLS_Client.ino. (When I modified the timer example to do the same thing, I did see the GPIOs toggle.) When I looked at the ucf file for the logic analyzer, it just had the 32 logic analyzer inputs and tx and rx. if I want to have additional GPIOs for use by Zpuino, do I need to modify the VHDL code for the wishbone logic analyzer? I am guessing the vanilla Zpuino defines all the GPIOs for use by Zpuino, but the Zpuino used by the logic analyzer takes some of this capability away. Blake
  8. Wishbone version of the Sump Blaze Logic Analyzer

    Hi Jack, It depends what you mean by getting it to work. I won't list all the tool issues I have that cause ISE to hang when launched from DesignLab, because I seem to have found ways to get around them. Where I stand now: 1) When I regenerate the bit file, it seems to be binary equivalent to the one that in the .zip file, which is encouraging. 2) The capture completes when I use the bit file and choose WB anything less than 256KB memory in the logic analyzer menu. However, when a feed a known frequency such as 100 KHz in, it thinks it is 66 KHz (at least in one attempt). When I load the regular logic analyzer bit file and choose Duo 64K, it correctly sees the frequency as 100 KHz. I am now going to look into the discrepancy. My plan is to add two GPIOs to the arduino sketch and toggle out all the values receive from the serial port, send to the serial port, and read from the wishbone bus out the two GPIOs in SPI fashion. Once I understand how the logic analyzer protocol works, I will start digging into the VHDL code. I will use my Papilio One in logic analyzer mode to view the GPIO toggles. Blake
  9. Wishbone version of the Sump Blaze Logic Analyzer

    Jack, Thanks for the quick reply. Before reading your reply, I changed the top level to BENCHY_sa_SumpBlaze_LogicAnalyzer32 and it successfully created the programming file. Blake
  10. Wishbone version of the Sump Blaze Logic Analyzer

    Hi Jack, When I tried to generate a programming file after setting wb_core as top module (which I think is what you suggested in the Back to Basics thread), it gets the following error when running the map: IO Utilization: Number of bonded IOBs: 192 out of 102 188% (OVERMAPPED) Is there something additional I need to do? Blake
  11. Back to Basics

    Thomas, Thank you for the suggestions. I will look into them. Jack, Thank you for showing me how to build the bit files. When I do this, I get the following errors: Parsing architecture <behavioral> of entity <benchy_wb_sumpblaze_logicanalyzer32>. ERROR:HDLCompiler:1314 - "/home/bn/sandbox/DesignLab-1.0.7/libraries/Wishbone_Sump_LA/BENCHY_wb_SumpBlaze_LogicAnalyzer32.vhd" Line 143: Formal port/generic <run> is not declared in <core> ERROR:HDLCompiler:432 - "/home/bn/sandbox/DesignLab-1.0.7/libraries/Wishbone_Sump_LA/BENCHY_wb_SumpBlaze_LogicAnalyzer32.vhd" Line 129: Formal <exttriggerin> has no actual or default value. INFO:HDLCompiler:1408 - "/home/bn/sandbox/DesignLab-1.0.7/libraries/Benchy/core.vhd" Line 55. exttriggerin is declared here ERROR:HDLCompiler:854 - "/home/bn/sandbox/DesignLab-1.0.7/libraries/Wishbone_Sump_LA/BENCHY_wb_SumpBlaze_LogicAnalyzer32.vhd" Line 49: Unit <behavioral> ignored due to previous errors. VHDL file /home/bn/sandbox/DesignLab-1.0.7/libraries/Wishbone_Sump_LA/BENCHY_wb_SumpBlaze_LogicAnalyzer32.vhd ignored due to errors As Thomas correctly points out, I will never get the hang of this until I put in the time to truly understand ISE, VHDL, and what is necessary to map this to the Papilio boards, so I will try to resolve these errors by myself. However, as Martin points, out, there are lots of very bright people who are not willing to go through all this just to see what FPGAs are all about. Blake
  12. Back to Basics

    Jack, I figured out how to "push into" BENCH_wb_SumpBlaze_LogicAnalyzer32, which allows me to see BENCHY_wb_SumpBlaze_LogicAnalyzer32.vhd. Is there a way to see all the vhdl files in the circuit, and recompile it like a normal .xise project, which would could then be loaded by DesignLab? Blake
  13. Back to Basics

    Jack, When I click on "edit circuit" today, it doesn't hang (maybe because I launched it from the command line the first time instead of just clicking on it in the GUI). The attached screenshot shows what I see. Can you explain to me how I "push into the Sump Blaze Logic Analyzer symbol to see the relevant code". Blake
  14. Back to Basics

    Jack, I can deal with any firmware issues since I have been coding low-level firmware professionally for decades. I am just having trouble with figuring out how I can write VHDL code that writes to the wishbone interface that the firmware can then read. To me, this would be the most powerful feature of your environment over straight VHDL, since one could use VHDL for things that firmware is not fast enough to handle, and use firmware for manipulating the data that the VHDL code sends to it at a more leisurely pace. I see how it is done in the schematic, but I find the schematic a hindrance (kind of like these visual programming languages that kids use on Mindstorms), and would really much rather just deal with VHDL. I wasn't aware that "edit circuit" was doing something besides just calling ISE. If you could help me solve this issue and that would allow me to compile the logic analyzer code in the ISE environment (which I am comfortable with), I would be very grateful. My development environment is Lubuntu 14.04 (I have other computers on 16.04, but since your development environment came out before 16.04, I didn't want to risk incompatibilities and deal with trying to get another license from Xilinx). I installed DesignLab and ISE on Windows 7 to see if this was a Linux issue, but from what I remember, I had even worse problems on Windows 7 (I don't have that computer with me, so I don't remember exactly what the issues were). As further comments on your back to basics, I would think it would be very useful if your site had more VHDL examples that were ported to your hardware, with lots of comments. Hamster has (or had since I read on it that he was going to take it down) a site with tons of examples, but many are for other boards, and the explanations are rather terse. Most of the examples on your site now start out with Arduino code, and then bolt some pre-written schematic code on, and also require the compute or game shield/wing (I only have the logicstart shield/wing). I know you have some tutorials on how to modify the schematics, but I would rather just cut to the chase and deal with VHDL. Don't get me wrong, I think your site is much better than any of the other FPGA sites that I have seen, and greatly appreciate all the effort you have put in, but when I run into trouble with DesignLab, I can't just search the web for answers like I do for everything else, and I haven't been able to find the answers in your examples, forum, and learning site. Blake
  15. Back to Basics

    For the example which I would really like to get work, I refer to the Feb 20 post that Jack made under the topic "Wishbone version of the Sump Blaze Logic Analyzer". When I click on edit circuit, ISE hangs, but I can see what it was trying to do, so I open I start ISE by itself and open the project that it hung on, which is DesignLab/OLS_Client/circuit/PSL_Papilio_DUO_LX9.xise. However, this project seems to have all the library code, not just that related to the Wishbone logic analyzer. Shouldn't there be a project that just has the Sump Logic analyzer project? What I really want to do is poke around and make modifications to the VHDL code in this project. Blake
  16. Back to Basics

    Jack, I have been very frustrated because I can't seem to get by the development environment hurdles, and my attempts to get help from you have not been successful. I have all but given up asking for help, and figure I will need to just figure out things by myself. The two things I tried unsuccessfully to get help from you are: 1) How to get your Wishbone version of the Sump Logic analyzer to compile without errors. I follow your instructions but it doesn't work. If I could just get this code to run, it would be a fantastic learning vehicle. 2) How to write VHDL code to write to the 2MB SRAM through the Wishbone interface so it can be read by the Zpuino. Also, when I try to build lots of the example projects, I get compilation errors. The bottom line is, I think your boards and resources are great, but the videos on your learn page are not enough for me to really become proficient enough to overcome the errors I get when trying examples that are supposed to work. By the way, will your new development environment support the old boards such as the DUO and 250K? Regards, Blake
  17. Communication over wishbone

    Jack, I ran through the Papilio DUO – AVR to ZPUino Communication over Wishbone example and it worked fine. However, it is not apparent to me how to access these same registers using vhdl. Could you show the changes that would be necessary for vhdl code to increment the register instead of the AVR, in which case the ZPUino code would will still see the register being incremented even if the AVR code was not running. Regards, Blake
  18. Communication over wishbone

    Jack, I just installed DesignLab 1.08 on a Windows 7 computer to see if I could avoid ISE hanging when I launch it from DesignLab. The installation of DesignLab and Xilinx ISE went fine, but when I tried to edit the AVR_to_ZPUino_Communications circuit, I got a popup that stated "Sorry, no Xilinx project file found in the libraries or project directory". I get the same message when I try to edit any circuit. How do I go about fixing this problem? Regards, Blake
  19. Communication over wishbone

    Jack, When do you think you will get time to answer my above questions? In the meantime, I found the following: and tried to implement it. When I tried to perform the following step: "To start, open DesignLab and select Papilio : New DesignLab Library – Wishbone VHDL to create the project. Change the name to BasicWishbone and click OK to save it." ISE hung. Can you give me a hint as to how I can stop ISE hanging when I do this? I then opened ISE alone and saw that it created BasicWishbone. I continued to follow all the steps, but when it came time to create the schematic symbol, it had the following errors: ERROR:HDLParsers:3317 - "/home/bn/DesignLab/libraries/BasicWishbone/Chip_Designer/../BasicWishbone.vhd" Line 24. Library DesignLab cannot be found. ERROR:HDLParsers:3014 - "/home/bn/DesignLab/libraries/BasicWishbone/Chip_Designer/../BasicWishbone.vhd" Line 25. Library unit DesignLab is not available in library work. due to the following statements in BasicWishbone.vhd: library DesignLab; use DesignLab.ALL; Can you tell me what I need to do so it can find the library DesignLab? Do I need to copy it somewhere, or is the result of New DesignLab call to ISE hanging and something not getting copied correctly? Regards, Blake
  20. Communication over wishbone

    Jack, I should have sent you this file instead of Papilio_DUO_LX9save5_works.sch as an example where the clocks work. Regards, Blake Papilio_DUO_LX9_works.sch
  21. Communication over wishbone

    Hi Jack, I have been trying out the steps you suggested, and I got them all to work. Thanks for the suggestions. Besides the original question of how to write to a wishbone register in VHDL, I have the remaining questions from my previous emails. 1) I could get clock input to the counter circuits by connecting clk_osc_32MHz to clk_32MHz (see the attached Papilio_DUO_LX9save5.sch). However, if I just created an IOB of clk_osc_32_MHz and connected it to clk_32_MHz, the wishbone register reads always read 0. Shouldn't these be equivalent? Also, when I tried to connect on IOB of clk to clk_32_MHz, it got the following error when I tried to generate the bit file (see the attached Papilio_DUO_LX9.sch). ERROR:Pack:2811 - Directed packing was unable to obey the user design constraints (LOC=P94) which requires the combination of the symbols listed below to be packed into a single IOB component. (I got the same error whether I made clk an input or output.) 2) What does connecting a wishbone register's input to its output do? When I don't connect the wishbone's register to its output, I still see the counter output that is connected to the wishbone register input when I read the wishbone register output. I also encountered the following annoyances. Whenever I opened ISE using edit circuit from DesignLab, ISE hung when I saved the .sch file after making changes. It did save the file though, so I could just end the ISE process and edit the circuit again to see my changes. To get around this annoyance, I would run ISE outside of Designlab, and just use Designlab to load the circuit. I also had to change the name of the generated bit file from Papilio_DUO_LX9.bit to papilio_duo_lx9.bit, since Designlab load circuit would only recognize it if it was in all lowercase. Regards, Blake Papilio_DUO_LX9save5_works.sch bfn_counter.vhd Papilio_DUO_LX9.sch
  22. Communication over wishbone

    Jack, When I try to add clk to the attached schematic, it complains with the following: Pack:2811 - Directed packing was unable to obey the user design constraints (LOC=P94) which requires the combination of the symbols listed below to be packed into a single IOB component. I don't see clk listed in the .pcf file that contains the net list, but somehow it knows that it is P94. I do see the following in the .pcf file: COMP "ext_pins_in<0>" LOCATE = SITE "P94" LEVEL 1; but when I tried to name the i/o connector ext_pins_in(0), it didn't like that either. So, what do I need to do to make the attached schematic output a 30 Hz signal on I/O pin Arduino8? Regards, Blake Papilio_DUO_LX9.sch
  23. Communication over wishbone

    Hi Jack, Could you provide a link to the example of creating a counter in the schematic editor? I don't see it on your learn site. Regards, Blake
  24. Communication over wishbone

    Jack, I don't understand what connecting the wishbone reg0 inputs to the wishbone reg 0 outputs does. Even when I disconnect reg 0 input from reg 0 output and apply vcc to one of the bits of the reg 0 input, I see it on that bit on the reg 0 output, so they still must be connected in some way. Could you explain the difference between the two scenarios? Regards, Blake
  25. Communication over wishbone

    Jack, The problem appears to be with creating the bus tap. When it didn't like it, the single bit of the bus tap was connected to vcc. When it did like it, the single bit of the bus tap was connected to one of the 32 bits of the wishbone register (i.e. both sides of the bus tap were connected to the same XLNX_ symbol). Another problem I had was that whenever I would save the schematic after changes, ISE would hang (I am using Lubuntu 14.04) and I had to end the process to gain control again. It does seem the changes were getting saved though, since when I edited the circuit again, I saw the changes. However, when I went into ISE directly and edited the circuit directly instead of pressing the edit circuit button in DesignLab 1.07 to edit the circuit, it would save my changes without hanging ISE. I will keep trying to carry out the experiments you suggested. Regards, Blake