bnusbick

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  1. Jack, I should have sent you this file instead of Papilio_DUO_LX9save5_works.sch as an example where the clocks work. Regards, Blake Papilio_DUO_LX9_works.sch
  2. Hi Jack, I have been trying out the steps you suggested, and I got them all to work. Thanks for the suggestions. Besides the original question of how to write to a wishbone register in VHDL, I have the remaining questions from my previous emails. 1) I could get clock input to the counter circuits by connecting clk_osc_32MHz to clk_32MHz (see the attached Papilio_DUO_LX9save5.sch). However, if I just created an IOB of clk_osc_32_MHz and connected it to clk_32_MHz, the wishbone register reads always read 0. Shouldn't these be equivalent? Also, when I tried to connect on IOB of clk to clk_32_MHz, it got the following error when I tried to generate the bit file (see the attached Papilio_DUO_LX9.sch). ERROR:Pack:2811 - Directed packing was unable to obey the user design constraints (LOC=P94) which requires the combination of the symbols listed below to be packed into a single IOB component. (I got the same error whether I made clk an input or output.) 2) What does connecting a wishbone register's input to its output do? When I don't connect the wishbone's register to its output, I still see the counter output that is connected to the wishbone register input when I read the wishbone register output. I also encountered the following annoyances. Whenever I opened ISE using edit circuit from DesignLab, ISE hung when I saved the .sch file after making changes. It did save the file though, so I could just end the ISE process and edit the circuit again to see my changes. To get around this annoyance, I would run ISE outside of Designlab, and just use Designlab to load the circuit. I also had to change the name of the generated bit file from Papilio_DUO_LX9.bit to papilio_duo_lx9.bit, since Designlab load circuit would only recognize it if it was in all lowercase. Regards, Blake Papilio_DUO_LX9save5_works.sch bfn_counter.vhd Papilio_DUO_LX9.sch
  3. Jack, When I try to add clk to the attached schematic, it complains with the following: Pack:2811 - Directed packing was unable to obey the user design constraints (LOC=P94) which requires the combination of the symbols listed below to be packed into a single IOB component. I don't see clk listed in the .pcf file that contains the net list, but somehow it knows that it is P94. I do see the following in the .pcf file: COMP "ext_pins_in<0>" LOCATE = SITE "P94" LEVEL 1; but when I tried to name the i/o connector ext_pins_in(0), it didn't like that either. So, what do I need to do to make the attached schematic output a 30 Hz signal on I/O pin Arduino8? Regards, Blake Papilio_DUO_LX9.sch
  4. Hi Jack, Could you provide a link to the example of creating a counter in the schematic editor? I don't see it on your learn site. Regards, Blake
  5. Jack, I don't understand what connecting the wishbone reg0 inputs to the wishbone reg 0 outputs does. Even when I disconnect reg 0 input from reg 0 output and apply vcc to one of the bits of the reg 0 input, I see it on that bit on the reg 0 output, so they still must be connected in some way. Could you explain the difference between the two scenarios? Regards, Blake
  6. Jack, The problem appears to be with creating the bus tap. When it didn't like it, the single bit of the bus tap was connected to vcc. When it did like it, the single bit of the bus tap was connected to one of the 32 bits of the wishbone register (i.e. both sides of the bus tap were connected to the same XLNX_ symbol). Another problem I had was that whenever I would save the schematic after changes, ISE would hang (I am using Lubuntu 14.04) and I had to end the process to gain control again. It does seem the changes were getting saved though, since when I edited the circuit again, I saw the changes. However, when I went into ISE directly and edited the circuit directly instead of pressing the edit circuit button in DesignLab 1.07 to edit the circuit, it would save my changes without hanging ISE. I will keep trying to carry out the experiments you suggested. Regards, Blake
  7. Hi Jack, When I connect wishbone register 1 (0:0) to vcc and then try to synthesize it, it complains with the following errors. Started : "Synthesize - XST". Running xst... Command Line: xst -intstyle ise -ifn "/home/bn/DesignLab/AVR_to_ZPUino_Communications/circuit/DUO_LX9/Papilio_DUO_LX9.xst" -ofn "/home/bn/DesignLab/AVR_to_ZPUino_Communications/circuit/DUO_LX9/Papilio_DUO_LX9.syr" Reading design: Papilio_DUO_LX9.prj ========================================================================= * HDL Parsing * ========================================================================= Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/zpu_config.vhd" into library work Parsing package <zpu_config>. Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/zpupkg.vhd" into library work Parsing package <zpupkg>. Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/zpuino_config.vhd" into library work Parsing package <zpuino_config>. Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/PSL_Papilio_DUO_LX9/zpuinopkg.vhd" into library work Parsing package <zpuinopkg>. Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/libraries/ZPUino_2/sram_ctrl8.vhd" into library DesignLab Parsing entity <sram_ctrl8>. Parsing architecture <behave> of entity <sram_ctrl8>. Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/libraries/ZPUino_2/pad.vhd" into library DesignLab Parsing package <pad>. Parsing entity <isync>. Parsing architecture <behave> of entity <isync>. Parsing entity <iopad>. Parsing architecture <behave> of entity <iopad>. Parsing entity <ipad>. Parsing architecture <behave> of entity <ipad>. Parsing entity <opad>. Parsing architecture <behave> of entity <opad>. Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/libraries/ZPUino_Wishbone_Peripherals/Wishbone_to_Registers_x10.vhd" into library DesignLab Parsing entity <Wishbone_to_Registers_x10>. Parsing architecture <rtl> of entity <wishbone_to_registers_x10>. Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/libraries/ZPUino_2/ZPUino_Papilio_DUO_V2.vhd" into library DesignLab Parsing entity <ZPUino_Papilio_DUO_V2>. Parsing architecture <behave> of entity <zpuino_papilio_duo_v2>. Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/libraries/Papilio_Hardware/Wing_GPIO.vhd" into library DesignLab Parsing entity <Wing_GPIO>. Parsing architecture <Behavioral> of entity <wing_gpio>. Parsing VHDL file "/home/bn/sandbox/DesignLab-1.0.7/libraries/Papilio_Hardware/Papilio_DUO_Wing_Pinout.vhd" into library DesignLab Parsing entity <Papilio_DUO_Wing_Pinout>. Parsing architecture <BEHAVIORAL> of entity <papilio_duo_wing_pinout>. Parsing VHDL file "/home/bn/DesignLab/AVR_to_ZPUino_Communications/circuit/DUO_LX9/Papilio_DUO_LX9.vhf" into library work Parsing entity <Papilio_DUO_LX9>. Parsing architecture <BEHAVIORAL> of entity <papilio_duo_lx9>. ERROR:HDLCompiler:806 - "/home/bn/DesignLab/AVR_to_ZPUino_Communications/circuit/DUO_LX9/Papilio_DUO_LX9.vhf" Line 537: Syntax error near "=>". ERROR:HDLCompiler:854 - "/home/bn/DesignLab/AVR_to_ZPUino_Communications/circuit/DUO_LX9/Papilio_DUO_LX9.vhf" Line 86: Unit <behavioral> ignored due to previous errors. VHDL file /home/bn/DesignLab/AVR_to_ZPUino_Communications/circuit/DUO_LX9/Papilio_DUO_LX9.vhf ignored due to errors --> Total memory usage is 111596 kilobytes Number of errors : 2 ( 0 filtered) Number of warnings : 0 ( 0 filtered) Number of infos : 0 ( 0 filtered) Process "Synthesize - XST" failed WARNING:ProjectMgmt - File /home/bn/DesignLab/AVR_to_ZPUino_Communications/circuit/DUO_LX9/Papilio_DUO_LX9.stx is missing. Could you tell me what I am doing wrong? I have attached the changed .sch file and generated .vhf file. Regards, Blake Papilio_DUO_LX9.sch Papilio_DUO_LX9.vhf
  8. Jack, I ran through the Papilio DUO – AVR to ZPUino Communication over Wishbone example and it worked fine. However, it is not apparent to me how to access these same registers using vhdl. Could you show the changes that would be necessary for vhdl code to increment the register instead of the AVR, in which case the ZPUino code would will still see the register being incremented even if the AVR code was not running. Regards, Blake
  9. Jack and Alvie, I would really like to try experiment with your Logic Analyzer implementation that uses DMA on a 2MB Duo. In an earlier message you said you didn't have DMA working but could simulate it, and in a later message you seemed to suggest that DMA is working. If I want to use your latest version, where should I get it, and what works and what doesn't? In your video, it is not using the OLS client, but instead is using an Zpuino program and the terminal. Is this still the way it works? Thanks, Blake
  10. Jack, I already have that source code. I am interested in the source code to the one that is included in Design Lab 1.0.7. Blake
  11. Hi Jack, Thanks, now I can get the original Logic Analyzer to work on the Duo. Since I can't get the one that you modified to work with the Zpuino to sample, could you point me to the source files that you based your Zpuino changes on, which I hope is the original one that works. Hopefully, by studying the differences I can see what changes are necessary to make it work with the Zpuino, and why there seems to be an issue. Thanks, Blake
  12. Correction--channel 0 is high and all the rest are low. Channel 0 is high even if I have nothing connected. Blake
  13. Jack, When I load the DesignLabs logic analyzer into my Papilio One 250K, it works fine. When I run the original DesignLabs logic analyzer into my Papilio Duo and connect 3.3 volts to the pin labeled MOSI-11, I still see all 32 logic analyzer pins all low (this is done with the AVR disabled). I am using DesignLab-1.0.7. Any suggestions? Thanks, Blake
  14. Jack, I am also having trouble getting the logic analyzer that comes with DesignLab to actually capture data. When I load it and an AVR program that just sends "Hello world" out at 115200 bps, I don't see any transitions on the logic analyzer. I know the AVR program is running since I can set it in the serial port monitor. In the logic sniffer I am selecting Papilio DUO -64K Memory. For acquisition I am choosing Sampling Clock Internal, Sampling Rate 1.000 MHz, Recording Size 64.00 kB. I cycled through Channel Group 0-3 one at a time each in four acquistions, and I didn't see any transitions on any of the channels. The capture is finishing, so it doesn't seem to be a communication problem. Do you have any ideas on what the problem can be? Thanks, Blake
  15. Jack, I too can't get this Wishbone logic analyzer to work for me. I am using libraries/Wishbone_Sump_LA/examples/OLS_Client.ino (after moving it to a new project). I had to make some modifications to it since the one in the .zip file does not compile without errors. It looks like you were changing how buffer was defined and actually have the diff markers in the file. I just changed buffer to be a defined as a 300000 entry 32-bit array. When I run the original Logic Analyzer that came with DesignLab, it can find the device on ttyUSB1, and it quickly fills up the buffer when I start the capture. However, when I download the the Wishbone one and select Papilio Duo-Wishbone Memory, and choose sampling rate of 2 MHz with recording size 128 KB, it just displays "Capture from OpenBench LogicSniffer started at ...". If I unplug the Duo board and plug it in again, it displays "Capture failed! Device not found!". Do you have any ideas why I am encountering these difficulties and have any suggestions on debugging them? I do have a 2MB Duo board. Thanks, Blake