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About Coolzire

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  1. I try a few thing and think I have isolated the problem. There seem to be a conflict when i try to use a internal SoC signal as an input for the ZPU i/o. ERROR:Xst:528 - Multi-source in Unit <Papilio_DUO_LX9> on signal <Arduino_50>; this signal is connected to multiple drivers. Drivers are: Output signal of BUFT instance <XLXI_44/pin00/PAD_I> <<= WAL0 Output signal of FDCE instance <XLXI_90/FlipflopD1/q> <<= My counter output
  2. Hi, I am working on a Soc and so far I have a counter incremented by the ZPU and 7Seg wishbone driver. I included a logic analyzer connected to counter output. Tonight I tried using a pin as an input connected to a debouncer. Regardless of the pin(D2,D3,D4 or D10) I use , I get an error because there is multiple driver. I cannot find any duplicated pin. I tried removing GPIO wing and it wires . The error message is : ERROR:Xst:528 - Multi-source in Unit <Papilio_DUO_LX9> on signal <XLXN_920>; this signal is connected to multiple drivers. Drivers are: Signal <XLXI_89/debounced_sig> is assigned to logic Signal <XLXI_44/Flex_Pin_out_5> in Unit <Papilio_DUO_Wing_Pinout> is assigned to GND I have tried following video where eight inputs are multiplexed into a bus then demuxed into 8 LED but I can't figure out. Anyone had a similar issue before? Thank in advance, -Olivier EDIT Added schematic pdf Schematic.pdf
  3. I got it working with the startup primitive. On my project pressing DIR_UP cause all flip-flop to return to their initial state. I included my VHDL code for the benefits of others. I instantiate my module with : HardReset : entity work.GlobalReset port map(DIR_UP); DIR_UP being the input used to trigger reset. -Olivier GlobalReset.vhd
  4. I checked your schematic and like the idea of using the AVR to generate a clock signal for the FPGA. As for the primitive , I am still trying to get it working. I managed to instantiate it in VHDL but my design was not functionning anymore. I am reading the datasheet to sort it out. -Olivier
  5. Thank for quick replies. It is exactly what I was looking for. I did manage to debounce my input with a synchronizer and a slow clock (400Hz). I'll implement the reset in my circuit and test it later today. -Olivier
  6. Hi Jack, I was doing a debouncing circuit with a counter making sure of a minimal pulse width. However I had an invalid state and my circuit would stop responding. I ended up unplugging/plugging the board to reset it while I was trying to debug the circuit. I just looking for a way to use a button from the shield to reset the FPGA as if i had pressed on the reset button on the board, if there is one. -Olivier
  7. Hi, I have been using y papilio duo for a while. My latest project had a issue and i needed to restart the FPGA. With the shield on top it is kinda difficult to reach the restart button. Is there a way to map one of the button to restart the FPGA? Thank in advance for your time , -Olivier
  8. Thank You for your hard work. I have been using my duo for some time and it really find it useful as logic analyzer.For example, I been able to figure out why my I2C sensor would only spit garbage and corrected my code. I have learned a lot about FPGA and I got a few simple projects running. I took a VLSI course last semester and could not advance because IT did not provide the Xilinx software until the fourth week. I found guide and videos on this website that explained everything I needed to start. Thank again, -Olivier
  9. Thank Jack for the help. I managed to open the project in edit mode whith Xilink ISE . I am seeing the wing are actualy C & D. I apologize, I had not selected the right board. I found the getting started videos and I added them my list. Thank again and Happy Holiday, -Olivier
  10. Hi, I purchased the papilio duo plus couple buffer wings and have a question. From what I understand the wing AH is missing from the board and the logic sketch use wings A and D.Is there a way to change the wing used by the stand alone logic analyser?. Upside is the AL wing is 5V tolerant. -Oilvier
  11. Hi, I am a computer engineering student looking to learn more about FPGA and I stumbled upon your products. I have a question regarding the wing buffer I/O . Currently I using a bus pirate with OLS software to debug my homework when all the measurement instrument are busy or I am at home. I looking to purchase a papilio duo and use a wing to get more I/O then the bus pirate. I have two questions: 1. I could use a Papilio Duo to thinker with FPGA and, with the buffer wings use it as a logic analyzer with the OLS software , right ? 2. What would be the measurement frequency of the said device ? I have looked through the forum and other website This gave me some information i was looking for:à Thank, -Olivier