gigcon

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  1. Thanks Felix and Jack.
  2. Hi Jack, It is Ubuntu 14.04 LTS, which is not the latest. Centos/Redhat 6.6 say reports the same -- just "linux".
  3. For those of you who might try to launch Logic Analyzer from DesignLab on Linux, let me share what I had to do to get that working. Although it is not very obvious from the getting-started video, the logic analyzer GUI should pop up automatically once the logic analyzer bit file is uploaded to Papilio. I was wondering if I had to do anything at this point because I wasn't seeing a window pop up. It eventually turned out that there were two problems in my case. 1. The OSTYPE environment variable is expected to be "linux-gnu", according to the script tools/Logic_Analyzer.sh, but it was "linux" in my case. You have the following at the very beginning of the script: # Simple check to see whether the "magic" Java binary is available on our path; if [[ "$OSTYPE" == "linux-gnu" ]]; then java -version 1>/dev/null 2>&1 else ../java/bin/java -version 1>/dev/null 2>&1 fi The "else" part is for Windows and some other platforms where JRE is bundled in the DesignLab installation. Since $OSTYPE == "linux" in my case, java didn't launch at all. 2. The java program is incompatible with Java version 1.8, but works with version 1.7. The JRE version that comes bundled with the windows version of DesignLab is version 7. In my case, java 1.8.0_91 was launched and it essentially hung after printing out lots of messages like the following: ERROR: Bundle nl.lxtreme.ols.tool.1wire [33] Error starting file:/home/puser/DesignLab-1.0.7/tools/ols-0.9.7/plugins/1wire-1.0.0.jar (org.osgi.framework.BundleException: Unresolved constraint in bundle nl.lxtreme.ols.tool.1wire [33]: Unable to resolve 33.0: missing requirement [33.0] osgi.wiring.package; (&(osgi.wiring.package=nl.lxtreme.ols.api)(version>=1.0.0)(!(version>=2.0.0))) [caused by: Unable to resolve 22.0: missing requirement [22.0] osgi.wiring.package; (osgi.wiring.package=nl.lxtreme.ols.util) [caused by: Unable to resolve 25.0: missing requirement [25.0] osgi.wiring.package; (osgi.wiring.package=javax.accessibility)]]) org.osgi.framework.BundleException: Unresolved constraint in bundle nl.lxtreme.ols.tool.1wire [33]: Unable to resolve 33.0: missing requirement [33.0] osgi.wiring.package; (&(osgi.wiring.package=nl.lxtreme.ols.api)(version>=1.0.0)(!(version>=2.0.0))) [caused by: Unable to resolve 22.0: missing requirement [22.0] osgi.wiring.package; (osgi.wiring.package=nl.lxtreme.ols.util) [caused by: Unable to resolve 25.0: missing requirement [25.0] osgi.wiring.package; (osgi.wiring.package=javax.accessibility)]] at org.apache.felix.framework.Felix.resolveBundleRevision(Felix.java:3826) at org.apache.felix.framework.Felix.startBundle(Felix.java:1868) at org.apache.felix.framework.Felix.setActiveStartLevel(Felix.java:1191) at org.apache.felix.framework.FrameworkStartLevelImpl.run(FrameworkStartLevelImpl.java:295) at java.lang.Thread.run(Thread.java:745) This is solved by changing references to java to /usr/lib/jvm/java-1.7.0-openjdk-amd64/bin/java. Once that's done, I get he logic analyzer GUI and it is working. Hope this helps. As a primarily-linux-based user, I seem to have many more hurdles to jump than an average windows user with DesignLab. I actually tried running on Windows as well, but at this point, I can't do anything as Windows 10 gives me the blue screen with NO_MORE_IRP_STACK_LOCATIONS error just a moment after I plug in Papilio at this. I know this is not a problem with papilio or the driver that comes with it, as I have used it successfully some time back. But for some reason, I am getting this crash now and haven't figured out how to fix it yet.
  4. Hi Jaxartes, Good catch! I can see that as well when programming my Papilio DUO. This is very convenient. Thank you.
  5. Is it possible to read the Device DNA on Xilinx Spartan 3E or 6 on Papilio boards? Thanks.
  6. Thanks for the reply, Jack. Yes, I'd perfectly understand if symptoms are that way. However, the original poster says the same limit of 12160 bytes applied to the Papilio One 500K board as well. That's what I don't understand. A fresh look at DesignLab/hardware/zpuino/zpu20/boards.txt file hinted that perhaps the original poster was using the Hyperion variant: zpuino_papilio_one250.name=Papilio One (250K) - ZPUino zpuino_papilio_one250.upload.maximum_size=12160 zpuino_papilio_one500.name=Papilio One (500K) - ZPUino zpuino_papilio_one500.upload.maximum_size=27648 zpuino_papilio_one500vps.name=Papilio One (500K) - ZPUino Hyperion zpuino_papilio_one500vps.upload.maximum_size=12160 This is now explained. Thanks a lot for the reply and for the great job you've done with the boards and the IDE.
  7. That'd be cool. Thanks, Alvie!
  8. Is there any way of increasing this limit of 12160 bytes? This was on Papilio one 250K board. When I tried the same sketch on Papilio DUO, it says "Sketch uses 15,176 bytes (0%) of program storage space. Maximum is 2,048,000 bytes." How much sketch space would a Papilio one 500K board would offer? Apparently the original post above mentions the limit of 12160 bytes for the 500K board. Why wouldn't it make any difference when the RAM/ROM capacity of the two are different? Is this limit imposed by the vanilla ZPUino implementation? Thanks.
  9. Hi Alvaro, Last time, I tried downloading from right here and the link didn't work. Then I found the version 2.0 code at githug and did clone git://github.com/alvieboy/ZPUino-HDL, cd to ZPUino-HDL/Papilio/papilio_one_250k_vanilla_ise and opened papilio_one_250k_vanilla_ise.xise from ISE. ISE complained "Source files in the project cannot be found (27). Those are: ZPUino-HDL/zpu/hdl/zpuino/{fifo,generic_dp_ram,pad,prescaler,shifter,spi,spiclkgen,timer,tx_unit,uart_brgen,wbarb2_1,wbmux2,wishbonepkg,zpu_core_extreme,zpuino_{crc16,empty_device,gpio,intr,io,sigmadelta,spi,timers,top,uart,uart_mv_filter,uart_rx,vga}}.vhd. Apparently,most of these files have been moved to different subdirectories, and maybe some are renamed? Today, I tried the download link on this page again, and I was able to download the version 1.0 source code. I could open the project with ISE successfully and it could generate the bit file just fine. Is version 2.0 supposed to be built this just like this as well? Or is it really broken? Thanks!
  10. I ran into the same problem. Unfortunately I didn't see this message before. Even the .bit file is not generated under the correct name. The generated file has the name Papilio_One_250K.bit, but what designLab expects is papilio_one_250k.bit.
  11. On linux ext file system, where capitalization matters, the Xilinx ISE project file circuit/PSL_Papilio_One_250K.xise has Upper case 'K', but the link in designLab the "New DesignLab Library" sketch template has " sketchdir://circuit/PSL_Papilio_One_250k.xise" with a lower-case 'K'. This results in an error when you invoke ISE by clicking on that link. Are these names coming from hardware/zpuino/zpu20/boards.txt? If so, other entries seem to have similar problems with .bit, .sch, and etc. files. Similar things happens with the .bit file. In the case of the .bit file, there's a default blank library already under the correct name, papilio_one_250k.bit. So when you think you're loading your circuit which is created under Papilio_One_250K.bit, the blank circuit is getting loaded. It took me some time to figure this out. I found, in the forum which I hadn't searched until now, others reporting similar problems as well. After spending so many hours jumping over these hurdles, I was finally able to use ZPUino with a wishbone peripheral of my own creation. Although I am complaining on usability and stiff learning curve, Papilio and DesignLab are still great stuff! Great Job, Jack!
  12. This download link is broken. And what I can download from github is missing some files. Is there a working source code? Thanks.