Rocker_Roller

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About Rocker_Roller

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  1. Thanks for the reply. Sounds good. ALso an other thing. I didnt want to start a separate thread for it. But I see that on the github page you have the eagle wings. However if I open it in eagle I see that I really cant edit them since they seem to be library components. Could you share the library you made for the OV7670 wing. Also the module seems to be 9x2 but you have only 8x2 connections. Why is this?
  2. Hi guys, I am not sure if this is the right forum to post in but lets say I want to create an I2C block on my FPGA. There are a lot of I2C blocks on opencores. Should I download these or does the design lab IDE do something similar. I need to be able to edit the VHDL code for these I2C blocks. Right now I still dont get exactly what Design Labs is doing. Is it just converting a hand drawn circuit to VHDL code? Are there any built in VHDL blocks that I can use(like open cores?). I don't want to use any C program and program the FPGA using C. The fpga is not a soft processor but operates as a standalone . AM I missing something?
  3. I was using the wrong spratn files.
  4. Hi , I downloaded the latest version of picoblaze and modified the older example. However I keep getting this message ERROR:NgdBuild:604 - logical block 'INST_UART_TX/next_lut' with type 'LUT6_2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6_2' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_TX/div23_lut' with type 'LUT6_2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6_2' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_TX/div01_lut' with type 'LUT6_2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6_2' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_TX/sm3_lut' with type 'LUT6' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_TX/sm2_lut' with type 'LUT6' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_TX/sm1_lut' with type 'LUT6' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_TX/sm0_lut' with type 'LUT6' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_TX/serial_lut' with type 'LUT6_2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6_2' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_TX/msb_data_lut' with type 'LUT6' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_TX/lsb_data_lut' with type 'LUT6' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_TX/full_lut' with type 'LUT6_2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6_2' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_TX/data_present_lut' with type 'LUT6_2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6_2' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_TX/pointer01_lut' with type 'LUT6_2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6_2' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_TX/pointer2_lut' with type 'LUT6' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_TX/pointer3_lut' with type 'LUT6' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_RX/sample_input_lut' with type 'LUT6_2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6_2' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_RX/div23_lut' with type 'LUT6_2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6_2' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_RX/div01_lut' with type 'LUT6_2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6_2' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_RX/start_bit_lut' with type 'LUT6' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_RX/run_lut' with type 'LUT6' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_RX/data67_lut' with type 'LUT6_2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6_2' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_RX/data45_lut' with type 'LUT6_2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6_2' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_RX/data23_lut' with type 'LUT6_2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6_2' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_RX/data01_lut' with type 'LUT6_2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6_2' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_RX/stop_bit_lut' with type 'LUT6_2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6_2' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_RX/sample_lut' with type 'LUT6_2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6_2' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_RX/full_lut' with type 'LUT6_2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6_2' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_RX/data_present_lut' with type 'LUT6_2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6_2' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_RX/pointer01_lut' with type 'LUT6_2' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6_2' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_RX/pointer2_lut' with type 'LUT6' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6' is not supported in target 'spartan3e'.ERROR:NgdBuild:604 - logical block 'INST_UART_RX/pointer3_lut' with type 'LUT6' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'LUT6' is not supported in target 'spartan3e'.UARTExample.vhd
  5. Hi, At the risk of sounding stupid I am going to write this anyway. The main aim of this project is the image manipulation(may be edge detection, or some other new algorithms for real time image improvement). The focus is on the algorithm development and not on the setup. I dont want to waste too much time setting this up). Would it be possible to obtain the image from a computer screen , lets say through a USB video camera which is available easily ,and would it be possible to get this setup running quicker. What I would like to do is transfer the data coming into the computer from the USB camera onto the FPGA. Then run the custom real time algorithms on the FPGA and send the data back either through HDMI or VGA to another device(Would it be possible to use the same USB port to send data back to the computer sending the data in? Would this make it easier?). -Also one of the restrictions on the project is that it should be written in verilog(It is an FPGA project after all, so the image manipulation tasks must be written in verilog. Is there any sample code anywhere that provides an idea as to how to work with images in verilog for the papilio(I understand that I would have to go in for the duo or pro since the papilio one doesnt have enough memory, but since I already have a papilio one would it be possible to get started with it.) Thanks a lot for the reply. I really was unsure about the direction in which I was to proceed.
  6. Do you know what are the limitation of ISE webpack. Can you write in Verilog or is it only VHDL? What are the restrictions?
  7. Hi guys, I need to do some manipulations on an image and would like to know if the approach I am following is correct. -I plan to use a Papilio one in order to write verilog code for the image manipulation tasks - The camera will most probably be the OV7670 and voelker has done a lot of work on it. I would most probably buy the wing along with the camera. I am assuming that interfacing the 2 would be straightforward since it has already been done. - Let say at a later point of time I want to increase my image resolution. What would be the ideal way to do this? I know interfacing USB is not possible . Does anyone have any other ideas? - How do I get the video out of the papilio one? I would like to display it on my TVdirectly. Is this possible or do I need to use the serial port of the papilio and send and receive data through this only? - Does the papilio one have enough processing power to do things like edge detection, overlay subtiles on an image etc Could someone please help me out?