MamboDee

Members
  • Content count

    2
  • Joined

  • Last visited

  • Days Won

    1

Community Reputation

1 Neutral

About MamboDee

  • Rank
    Newbie

Profile Information

  • Gender Not Telling
  1. Thanks everyone for the replies. Sorry to make you wait. It turned out to be my logic analyser was not keeping up. I went out and got a Digilent CMod S6. This board runs at 8MHz. After loading the same exact same code, the wave form came out as expected. I then did some research and loaded up the papilio pro with a DCM that cuts the speed down to 8MHz. The papilio pro works like a champ also. After some frustrating math and and trying to figure out how the world works, it turns out the 62.5ns pulse width combined with the slight difference in speed between the oscillator of the board and the logic analyser caused a rolling variation of just enough for the samples to catch the pulses for a few ticks and then miss for a few ticks. A lesson learned indeed. Some notes: Yes, I had a reset and the counter was initialized. All the extra trimmings were in the tutorial code. But when the results were not as expected, I wanted to remove as much as possible while trying to troubleshoot the issue. My logic analyser is the Saleae Logic (the first one). It only works reliably up to 16Msps on my pc. I thought 16Msps would be good enough, but after this adventure, I think I can talk my wife into letting me get one of the new models Thanks again, and please forgive my noobness. Gotta start somewhere.
  2. I am new the FPGA and picked up a Papilio Pro. Going through a tutorial I found, I am attempting to create a pulse generator. My code is as follows: library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity pulse_gen is Port ( CLK_SYS : in STD_LOGIC; CLK_OUT : out STD_LOGIC);end pulse_gen;architecture Behavioral of pulse_gen is signal sample_counter: std_logic_vector(7 downto 0);begin sample_process: process (CLK_SYS) is begin if rising_edge(CLK_SYS) then if sample_counter = 207 then CLK_OUT <= '1'; sample_counter <= (others => '0'); else CLK_OUT <= '0'; sample_counter <= sample_counter + 1; end if; end if; end process;end Behavioral;Seems simple enough. This should generate a steady stream of pulses by counting up to 207 then resetting to zero and counting again. However, when logic probing to see the results after loading to the board, I am not getting a steady stream. What I get is about 80 to 81 62.5nS wide pulses (6.5uS period) followed by 656.5uS of no activity (low signal). The pattern just repeats, a stream of about 80 or so pulses then low signal. The 6.25nS width makes sense. 35MHz = 31.25nS Period. 31.25x2 accounts for the 2 clock cycles for the signal to go high and low again, as described in the sample_process. And the period of the pulses measured at 6.5 uS, can be explained by 207 x 31.25 = 6,468.75nS. Close enough (I think). But I cannot explain the 656.5 of no output between the pulse groups.