Hi everyone,
I have a beginner question about VHDL processes. Let's say, for the sake of argument, I want to synthesize something like a TTL 7400 chip (i.e. quad nand gate). An initial attempt might involve doing something like this:
process(A1, A2, A3, A4, B1, B2, B3, B4)
begin
Y1 <= A1 nand B1;
Y2 <= A2 nand B2;
Y3 <= A3 nand B3;
Y4 <= A4 nand B4;
end process;
It would seem to me that the long dependency list wouldn't make this terribly efficient, at least not during simulation, and that ideally processes should maybe try to do something like this:
process(A1, B1)
begin
Y1 <= A1 nand B1;
end process;
process(A2, B2)
begin
Y2 <= A2 nand B2;
end process;
// ...etc...
So my first question is "am I correct in my understanding of this?", i.e. is it indeed a good idea in general to separate logic into different processes like this? Or is there some overhead associated with processes that makes it inadvisable for simple cases? And if so, where's the cross-over point?
Or should I forget about focusing so much on simulation and instead concentrate on trying to help synthesis? E.g. something like this...
-- A, B and Y are now all std_logic_vector(3 downto 0)
process(A, B)
begin
Y <= A nand B;
end process;
...which technically is the same as my first example above (I think) but would usually wind up in a more efficient circuit (I think)?
I hope these questions aren't too vague, just trying to get my head around best practices. Thanks in advance for any advice and general guidance.