Tony Ivanov

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About Tony Ivanov

  • Birthday 01/02/1970

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  1. ... I solved it!! Damn i feel so stupid. I had accidentally connected the Output->Output and Input->Input... Damn Flipped the connections and now everything works as expected. Big thanks to you Alvie! I'd later wish to learn how you Loaded up the generated-schematic or what file you opened to produce that image that showed the final schematic. Huge thanks for the help!
  2. So here's a summary of what Alvie found by looking at the generated files. He traced it to the schematic where it's clearly visible that the wishbone bus of the wing is not connected to anything, But in my schematic it looks like this: Super wierd.. o_o Anyways, Alvie asked me to forward my current state of project-folder to you @Jack Gassett. I uploaded the whole wing folder here, if you have time: https://www.dropbox.com/s/l18lyfrvpmfs11m/DSP_Wing.zip?dl=0 ~ 7mb. Meanwhile I'm gonna try and delete the wishbone connections and reconnect them, maybe it's just some graphical glitch that makes it look as if they're connected.. (hopefully not, that's a little bit scary) Regards /Tony
  3. Yeah that's basically the current state of the sourcecode, If that bit just gets flipped to a 1 then the audible effect should kick in. Funny! That thought hit me an hour ago, I guess it should be possible with some adaption to rewire the logic analyzer wing in the Designlab-examples to listen on internal signals instead of external pins.
  4. Thank you Jaxartes! Stupid as it may seem i did't actually consider connecting lots of leds for debugging purpose, since duplicating signal output to an alternative led is quite easy. (Soldering a small 8led wing might be the next project) Well yes basically I wanted to know if there was any way to read the current state of registers using the JTAG bus or something, getting the power of a logic-analyzer but without connecting any external hardware. But nevermind that now, I guess papilio debugging is a completley different topic. As for the lockups, yeah I've quadruple checked that the wing is connected to wishbone-slot 6 and that the c/c++ on the zpuino tries to use the same slot. But I suppose that even if I wrote to the wrong wishbone slot then It shouldn't cause a complete ZPUino lockup?
  5. I gathered up all i could find and just sent it to you, but i'm afraid i forgot to enable detailed map report, will have to send it separately. Thank you EDIT: Activated detailed map-report, regenerated and resent. This is the first time in my life that someone who wanted to help me debug a problem asked for the compiled binaries instead of the source, hehehe. Speaking of debugging, there isn't a way to attach a debugger to a running FPGA in order to inspect its internal state right? Or something along those lines.. I haven't quite yet figured out how to troubleshoot my own designs.
  6. It might be worth mentioning that i created this project in DesignLab 1.0.2's template , maybe I should migrate my code to the 1.0.7 template?
  7. Wow big thanks for your time Jack! Yeah I'm really looking forward to the new product, It's a must have and great job! Yep that's the line that freezes the ZPUino. REGISTER(IO_SLOT(wishboneSlot),REG_FX_CTRL) = ((value & 0xff) << 9) | ( (param & 0xf) << 5 ) | ( (fx & 0xf) << 1) | 1; , the sound from the ADC to the AudioWing continues happily as if nothing ever happened, I can try and just write a shorter or simpler value to the register to see If i get different results, or maybe try to write to a different register, it shouldn't matter if i use Register0 or 1/2 right? ( Also when i resynthesize with the tremolo effect hardcoded to enabled it's heard loud and clear, so I kindof almost ruled out that the issue is in the VHDL code. ) Let me get back a little bit later with the .ncd/ngd/syr files, I don't have access to my workdesk right now. I don't think I recognize those files but I assume they're artifacts produced during the synthesis process? I'll take a look in my project folder as soon as i can.
  8. Hi! I'm trying to create a library based on the "Wishbone VHDL" sample i think. I'm currently stuck trying to write to a wishbone register, the ZPUIno just locks up while the vhdl-module continues to happily tick without any noticeable changes. I've cross-referenced my code with the simple writeLeds example but I really can't see anything that should cause this lockup, please help!. ( btw I'm on an Papilio Pro board ) Here's my code: I can see the print of line 13 just fine, line 14 initiates the write, and then it gets stuck and I never seems to reach line 15 https://github.com/telamon/papilio-dspwing/blob/865e322b7eb3d761216595fead3c85fb294811ed/examples/simple_tremolo/simple_tremolo.ino#L15 which goes to: https://github.com/telamon/papilio-dspwing/blob/865e322b7eb3d761216595fead3c85fb294811ed/DSP_Wing.cpp#L33 <- how i perform the actual register write https://github.com/telamon/papilio-dspwing/blob/865e322b7eb3d761216595fead3c85fb294811ed/DSP_Wing.vhd#L98 <-- Here i try to receive/read. and finally.. https://github.com/telamon/papilio-dspwing/blob/865e322b7eb3d761216595fead3c85fb294811ed/tremolo.vhd#L68 <-- unpack and act upon the command. but that never happens either, so i can only assume that something went wrong with the register write inside the zpuino and that the changes to the register were never applied. Best Regards /Tony