Tony Ivanov

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About Tony Ivanov

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  • Birthday 01/02/1970

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  1. well with cheap modules like that we don't need a custom wing design. Ordered a similar module from ali (around 13$) and now begins the long wait xD
  2. What do you think of this module? I just quickly eyed the specs and it looked to provide up to 32bit sound?
  3. Wait you mean i can use this directly? I was under the impression that I couldn't use the controller directly as it was already assigned to the ZPUino-core, I don't quite yet understand all the factors but my guess was that I had to go through the DMA channel in order to reserve a few bytes of memory for my VHDL-module and avoid overwriting sections used by ZPUino. But maybe i got it wrong and the DMA-interface is only needed if i want to access the same memoryspace with C/C++ and VHDL at the same time? Hehe yeah you're completley right, great input! I think with real codec wing it shouldn't be that much more of a problem to widen the audio bus to 20+ bits?
  4. ... I solved it!! Damn i feel so stupid. I had accidentally connected the Output->Output and Input->Input... Damn Flipped the connections and now everything works as expected. Big thanks to you Alvie! I'd later wish to learn how you Loaded up the generated-schematic or what file you opened to produce that image that showed the final schematic. Huge thanks for the help!
  5. So here's a summary of what Alvie found by looking at the generated files. He traced it to the schematic where it's clearly visible that the wishbone bus of the wing is not connected to anything, But in my schematic it looks like this: Super wierd.. o_o Anyways, Alvie asked me to forward my current state of project-folder to you @Jack Gassett. I uploaded the whole wing folder here, if you have time: ~ 7mb. Meanwhile I'm gonna try and delete the wishbone connections and reconnect them, maybe it's just some graphical glitch that makes it look as if they're connected.. (hopefully not, that's a little bit scary) Regards /Tony
  6. Yeah that's basically the current state of the sourcecode, If that bit just gets flipped to a 1 then the audible effect should kick in. Funny! That thought hit me an hour ago, I guess it should be possible with some adaption to rewire the logic analyzer wing in the Designlab-examples to listen on internal signals instead of external pins.
  7. Thanks! I was actually quite impressed with the audio-quality I got out of the cheap 12bit ADC i'm currently experimenting with but the wing that fantasma designed should produce an even more intresting bitstream. Ah! Actually I've been meaning to find out how much samples I'd be able to store using BRAM alone. The papilio pro comes with an 64mbit Sdram as well which i've been trying to figure out how to access. Offtopic: I figured from some other threads that It should be possible to store/read samples in SDRAM by interfacing to the bus denoted as "VGA DMA" on wishbone slot 14 on the ZPUino schematic, the reason for including the ZPUino in my project instead is to separate the complexity into 3 different areas of expertise - someone to design the wings, someone to engineer effects in vhdl and someone to create avantgarde user-interfaces from sensors . But yeah as you said trying to accomplish a complete FPGA-DSP solution in one go would probably require a tremendous effort, and it might not even be portable or adaptable enough to gain popularity. Having said all that I feel a bit silly because I often feel myself quite lacking in all three areas, hehehe. But hey, it's always fun to learn something new.
  8. Wow great insight @offroad! So basically the reason I ever found Papilio was that I realized that no matter what pocket-sized diy-device I work with theres going to be problems with latency as long as the actual audio-processing takes place in software, so FPGAs felt like a natural step. Well I've already kindof realized that frequency analysis is quite a pain and there are quite a few limits compared to the retail guitar sound solutions. But regardless of fact, It's been a great learning experience and even if I never achieve HiFi sound modeling, I believe that because of the size,price and the connectivity/interfacing potential you get, you should still be able to explore some interesting new venues as far as musical-toys go. The current goal is to implement volume based effects like tremolo, and next step is to explore the delay based effects like Echo and Looper, which i think shouldn't require more than the ability to store away samples that can be replayed later. I haven't yet done my research if there are any cheap external IC's with filtering capabilities that could offload the FPGA. But still the main Idea is to let the actual audio-stream flow through realtime-logic while the non-vital control-logic can run on the soft-processor - Basically a revamp of the Retrocade Synth for guitarists What do you think?
  9. I'm intrigued, i'm working on something similar but haven't quite put as much effort in designing a real wing with high quality audio. Basically an audio-in wing is what I feel is i missing in the Gadetfactory wing-section, something to acompany the current sigma-delta dac AudioWing. I know it's gone a couple of years since you originally made this post, but did you make any progress or found something else to fill the function? I really liked the specs of this module: It even had a built in preamp for microphone/passive audio emitters, but to be frank, it's not a Papilio wing and that is a huge obstacle for newcomers who want to focus on the software-design of their applications. It took me atleast a year of on-and-off project shelving to just get the audio to flow through the papilio, if I only had access to such a wing back then...
  10. Thank you Jaxartes! Stupid as it may seem i did't actually consider connecting lots of leds for debugging purpose, since duplicating signal output to an alternative led is quite easy. (Soldering a small 8led wing might be the next project) Well yes basically I wanted to know if there was any way to read the current state of registers using the JTAG bus or something, getting the power of a logic-analyzer but without connecting any external hardware. But nevermind that now, I guess papilio debugging is a completley different topic. As for the lockups, yeah I've quadruple checked that the wing is connected to wishbone-slot 6 and that the c/c++ on the zpuino tries to use the same slot. But I suppose that even if I wrote to the wrong wishbone slot then It shouldn't cause a complete ZPUino lockup?
  11. I gathered up all i could find and just sent it to you, but i'm afraid i forgot to enable detailed map report, will have to send it separately. Thank you EDIT: Activated detailed map-report, regenerated and resent. This is the first time in my life that someone who wanted to help me debug a problem asked for the compiled binaries instead of the source, hehehe. Speaking of debugging, there isn't a way to attach a debugger to a running FPGA in order to inspect its internal state right? Or something along those lines.. I haven't quite yet figured out how to troubleshoot my own designs.
  12. It might be worth mentioning that i created this project in DesignLab 1.0.2's template , maybe I should migrate my code to the 1.0.7 template?
  13. Wow big thanks for your time Jack! Yeah I'm really looking forward to the new product, It's a must have and great job! Yep that's the line that freezes the ZPUino. REGISTER(IO_SLOT(wishboneSlot),REG_FX_CTRL) = ((value & 0xff) << 9) | ( (param & 0xf) << 5 ) | ( (fx & 0xf) << 1) | 1; , the sound from the ADC to the AudioWing continues happily as if nothing ever happened, I can try and just write a shorter or simpler value to the register to see If i get different results, or maybe try to write to a different register, it shouldn't matter if i use Register0 or 1/2 right? ( Also when i resynthesize with the tremolo effect hardcoded to enabled it's heard loud and clear, so I kindof almost ruled out that the issue is in the VHDL code. ) Let me get back a little bit later with the .ncd/ngd/syr files, I don't have access to my workdesk right now. I don't think I recognize those files but I assume they're artifacts produced during the synthesis process? I'll take a look in my project folder as soon as i can.
  14. Hi! I'm trying to create a library based on the "Wishbone VHDL" sample i think. I'm currently stuck trying to write to a wishbone register, the ZPUIno just locks up while the vhdl-module continues to happily tick without any noticeable changes. I've cross-referenced my code with the simple writeLeds example but I really can't see anything that should cause this lockup, please help!. ( btw I'm on an Papilio Pro board ) Here's my code: I can see the print of line 13 just fine, line 14 initiates the write, and then it gets stuck and I never seems to reach line 15 which goes to: <- how i perform the actual register write <-- Here i try to receive/read. and finally.. <-- unpack and act upon the command. but that never happens either, so i can only assume that something went wrong with the register write inside the zpuino and that the changes to the register were never applied. Best Regards /Tony
  15. Wow thanks Filip, that helped! I did't know that the red squares were the actual connectors and the rest of lines were just plain graphics.