hib1

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About hib1

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  1. Mike, I am getting the following error messages for the top level for using two counters in one design. Please suggest a solution. ERROR:NgdBuild:604 - logical block 'counter1' with type 'counter30' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'counter30' is not supported in target 'spartan3e'. ERROR:NgdBuild:604 - logical block 'counter2' with type 'counter30' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'counter30' is not supported in target 'spartan3e'. .
  2. Thanks Mike, I will try it when I get back from travel in 5 days. Howard
  3. In the FPGA book “Introducing the Spartan 3E FPGA and VHDL” by Hamster the Project 10.7, Binary up counter, does not give any VHDL code. It says “Using the above template, extend the project to use a 30-bit counter ("29 downto 0"), displaying the top 8 bits on the LEDs”. Does anyone have VHDL code for this or a similar counter that will display data on LEDs on the Logic Start board or on pins of the Papilio One?
  4. Thanks to all for the detailed explanations.
  5. I found a missing line in the vhd file. The project works now. Sorry for the trouble I may have caused.
  6. I am using a Papilio one 500 and the logic start one board. I tested the logic start with the test program that exercise all of the leds and switches and every worked. I programmed the same boards with the program "first project" in the book "Introducing the Spartan 3E FPGA and VHDL" by Hamster. I cut and pasted the code and the project built and generated a bit file. No LEDs lit when I moved all of the switches. Does anyone have suggestions on getting this first project to work?
  7. I am asking about a specific piece of code that is already written and is in a VHDL book. In the ucf file I do not see how the pin numbers are defined for the logic start board. They are only termed NET switch_1, etc. How does this allow me to generate a bit file without additonal information about the logicstart board pins? The entire ucf file is this. how are the logicstart board pins identifed in these 4 lines of code? NET switch_1 LOC = "P3" | IOSTANDARD=LVTTL; NET switch_0 LOC = "P4" | IOSTANDARD=LVTTL; NET LED_1 LOC = "P16" | IOSTANDARD=LVTTL; NET LED_0 LOC = "P17" | IOSTANDARD=LVTTL;
  8. Looks good. Did you interface the wi-fi using ZPUino?
  9. I am following the intro to spartan fpga book “first project” involving papilio one and a logicstar megawing with switches and leds. The constraints file is: # Constraints for Papilio One NET switch_1 LOC = "P3" | IOSTANDARD=LVTTL; NET switch_0 LOC = "P4" | IOSTANDARD=LVTTL; NET LED_1 LOC = "P16" | IOSTANDARD=LVTTL; NET LED_0 LOC = "P17" | IOSTANDARD=LVTTL; This is mapping each led or switch on the logic start board to a pin on the papilio board. The pin numbers on the papilio are defined, but the pins on the logic start board are not. How can this work?
  10. I am using the Xilinx ISE design tool 14.7. In order to fill in the "Project Settings" form in the "New Project Wizard" I need to I find all of the Project settings for the 3 different Papilio boards (family, device, package, speed, etc.)? I cannot find these values on this website. Also, is a template available for each in the "Evaluation Development Board" dropdown menu?
  11. Thanks for the quick response. Is a bus LED actually multiple LEDs addressable by separate bits?
  12. I raised this question earlier but received no replies re: "Introducing the Spartan 3E FPGA and VHDL." Please tell me what is the difference is between the UCF notation with < > symbols vs. the notation with " " symbols? notation 1 is in book, but notation 2 is in some other sample code I received. Also, it appears that "IOSTANDARD=LVTTL" is not required. notation 1 from the book:NET LED_1 LOC = "Pxx" | IOSTANDARD=LVTTL;NET LED_0 LOC = "Pyy" | IOSTANDARD=LVTTL; notation 2:NET "LED<1>" LOC="Pxx" NET "LED<0>" LOC="Pyy"
  13. Hello Mike, I created "Chapter 6 Your first project" on my Papilio Pro using your E-book. I was unable to get this e-book project to perform. I noticed in your book the UCF is # Constraints for Papilio OneNET switch_1 LOC = "P3" | IOSTANDARD=LVTTL;NET switch_0 LOC = "P4" | IOSTANDARD=LVTTL;NET LED_1 LOC = "P16" | IOSTANDARD=LVTTL;NET LED_0 LOC = "P17" | IOSTANDARD=LVTTL; However there is different notation in the UCF you sent me for the Papilio Pro project "Pro_button_led" that you sent me and that you included earlier in this thread: NET "LED<1>" LOC="P98" ; # A14 NET "LED<2>" LOC="P88" ; # A12 NET "BTN<1>" LOC="P100" ; # A15 NET "BTN<2>" LOC="P93" ; # A13 I also changed LED<1> to LED <0> and LED<2> to LED<1>and the same changes for buttons 1 and 2. I still no had no success. What is the difference between the UCF notation with < > symbols vs. the notation with " " symbols?Also, it appears that "IOSTANDARD=LVTTL" is not required. If you could tell me what the correct UCF is for this lesson I would appreciate it. Then I can proceed to other lessons in your book, once I learn this item.
  14. Very nice. Another incentive to install Zpuino and learn VHDL.