Haider

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  1. Hi, Yesterday I received my new Papilio Pro which ordered from Seeedstudio to my postal box in USA then ship it to IRAQ I'm really happy with the new Board and LogicStart MegaWing Now I'm an official member in this forum
  2. I make the change and this is my UCF file ## Clock signalNET "clk" LOC = "V10" | IOSTANDARD = "LVCMOS33"; #Bank = 2, pin name = IO_L30N_GCLK0_USERCCLK, Sch name = GCLKNet "clk" TNM_NET = sys_clk_pin;TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 25000 kHz;## VGA ConnectorNET O_VIDEO_R<0> LOC = "U7" | IOSTANDARD = "LVCMOS33"; NET O_VIDEO_R<1> LOC = "V7" | IOSTANDARD = "LVCMOS33"; NET O_VIDEO_R<2> LOC = "N7" | IOSTANDARD = "LVCMOS33"; NET O_VIDEO_G<0> LOC = "P8" | IOSTANDARD = "LVCMOS33";NET O_VIDEO_G<1> LOC = "T6" | IOSTANDARD = "LVCMOS33";NET O_VIDEO_G<2> LOC = "V6" | IOSTANDARD = "LVCMOS33";NET O_VIDEO_B<0> LOC = "R7" | IOSTANDARD = "LVCMOS33";NET O_VIDEO_B<1> LOC = "T7" | IOSTANDARD = "LVCMOS33";NET "Hsync" LOC = "N6" | IOSTANDARD = "LVCMOS33"; NET "Vsync" LOC = "P7" | IOSTANDARD = "LVCMOS33"; #NET "vgaRed<0>" LOC = "U7" | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L43P, Sch name = RED0#NET "vgaRed<1>" LOC = "V7" | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L43N, Sch name = RED1#NET "vgaRed<2>" LOC = "N7" | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L44P, Sch name = RED2#NET "vgaGreen<0>" LOC = "P8" | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L44N, Sch name = GRN0#NET "vgaGreen<1>" LOC = "T6" | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L45P, Sch name = GRN1#NET "vgaGreen<2>" LOC = "V6" | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L45N, Sch name = GRN2#NET "vgaBlue<1>" LOC = "R7" | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L46P, Sch name = BLU1#NET "vgaBlue<2>" LOC = "T7" | IOSTANDARD = "LVCMOS33"; # Bank = 2, Pin name = IO_L46N, Sch name = BLU2I try both this like TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 25000 kHz;and nothing change, I got black screen everytime so is there problem in adjusting the Clock Frequency or there is another way to write it?
  3. I think the same thing will happen with Papilio Pro if I want to Implement this code on it, Pro has also 3 Pins for Red, Green and 2 for Blue. NET VGA_BLUE(0) LOC="P92" | IOSTANDARD=LVTTL; # B2NET VGA_BLUE(1) LOC="P87" | IOSTANDARD=LVTTL; # B3NET VGA_GREEN(0) LOC="P84" | IOSTANDARD=LVTTL; # B4NET VGA_GREEN(1) LOC="P82" | IOSTANDARD=LVTTL; # B5NET VGA_GREEN(2) LOC="P80" | IOSTANDARD=LVTTL; # B6NET VGA_RED(0) LOC="P78" | IOSTANDARD=LVTTL; # B7NET VGA_RED(1) LOC="P74" | IOSTANDARD=LVTTL; # B8NET VGA_RED(2) LOC="P95" | IOSTANDARD=LVTTL; # B9Rhe source code for Nexys 3 board in the attachment, vga7seg.zip
  4. Hi Jack Gassett, if you don't mind could you take a look in this thread. http://forum.gadgetfactory.net/index.php?/topic/2558-need-little-help-to-implement-this-virtual-7-segment-display-on-vga/
  5. Sorry I didn't realize this thread before 3 years ago , when I read the title I was so enthusiastic to read it and ask my questions .
  6. The original source code got it from this link but there is some problem to download it so I suggest to download it from the attachment, I didn't make any change, http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/logicstart-megawing/virtual-7-segment-display-on-vga-r37 Also I upload the UCF file for Nexys 3 board to make the code work on Nexys3 nexys3_master_ucf.zip vga7seg-master.zip
  7. with this change begin -- connect internal video signals to outputs VideoR <= O_VIDEO_R(0) & O_VIDEO_R(1) & O_VIDEO_R(2); VideoG <= O_VIDEO_G(0) & O_VIDEO_G(1) & O_VIDEO_G(2); VideoB <= O_VIDEO_B(0) & O_VIDEO_B(1);I get this ERROR:HDLCompiler:288 - "C:\vga7seg\source\seven_segment_top.vhd" Line 46: Cannot read from 'out' object o_video_r ; use 'buffer' or 'inout'ERROR:HDLCompiler:288 - "C:\vga7seg\source\seven_segment_top.vhd" Line 47: Cannot read from 'out' object o_video_g ; use 'buffer' or 'inout'ERROR:HDLCompiler:288 - "C:\vga7seg\source\seven_segment_top.vhd" Line 48: Cannot read from 'out' object o_video_b ; use 'buffer' or 'inout'ERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 97: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 98: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 99: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 100: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 101: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 102: Indexed name is not a std_logic_vectorERROR:HDLCompiler:854 - "C:\vga7seg\source\seven_segment_top.vhd" Line 23: Unit <rtl> ignored due to previous errors.and this change begin -- connect internal video signals to outputs O_VIDEO_R <= VideoR(0) & VideoR(1) & VideoR(2); O_VIDEO_G <= VideoG(0) & VideoG(1) & VideoG(2); O_VIDEO_B <= VideoB(0) & VideoB(1);give me different errors (less errors ) ERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 97: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 98: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 99: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 100: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 101: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 102: Indexed name is not a std_logic_vectorERROR:HDLCompiler:854 - "C:\vga7seg\source\seven_segment_top.vhd" Line 23: Unit <rtl> ignored due to previous errors.
  8. Hi, I read the title of this thread and enter to see ... I'd like to take a place in this discussion if you don't mind please, I have the same question about FPGA, before I start learning FPGA I was playing with MCU like AVR, Parallax Propeller 8 core I understand C/C++ and can implement any idea in embedded system device, I move to FPGA because I read in some of university program for MSc there is FPGA lectures in Embedded system course beside MCU lectures, I want to know the reason so that's why start learning FPGA and buy my first FPGA, but to be honest with you i don't want to learn something for fun only I want to love it and be an expert in that field to get professional job in the future, All what I see in this form is re implement some of exist hardware chip on FPGA like ZPUino or other circuit, there is no new invention forget that let’s talk about professional member in this forum like Alvie or Hamster the programming FPGA at least before 10 year ago and everyone is expert in FPGA what is the best thing that they did, Alvie if I'm not wrong make the ZPUINO and its Re-implement of ZPU soft core, Hamster make the FPGA board and provide FPGA lecture in his website,if we want to convert the ZPUINO into ASIC chip it will never be a competitor against Atmel328p I can’t imagine the Energy consumption and number of Transistors in ZPUNIO is much more and it's need a lots of optimizing, if these people with their experience can't make chip like Atmel328p so why the spend their time to continue using FPGA, also how about person like me who start from scratch trying to be successful FPGA engineer, I Understand FPGA not using only in ASIC Design, can someone tell me anyone in this forum have a job deals with FPGA, if there is no problem can I ask about Hamster job or Alvie are they FPGA engineer in real life or their job is difference and they learn FPGA and become professional for fun only, I want to ask this question and many other question before long time because I'm so Confuse between choosing the right direction for my future work and field, I Believe if someone want to be successful in something then he should become a specific in that field not Embedded System programmer in C/C++ and FPGA engineer VHDL and Verilog in the same time, I believe the professional engineer in NXP, Nvidia, Samsung, everyone has his specific job and don't deal with other who have difference job, if anyone have another idea or I say something wrong I will be so interesting to know his opinion about what I say.
  9. I deactivate this lines begin -- connect internal video signals to outputs O_VIDEO_R <= VideoR; O_VIDEO_G <= VideoG; O_VIDEO_B <= VideoB;and make this changes begin -- connect internal video signals to outputs --O_VIDEO_R <= VideoR; --O_VIDEO_G <= VideoG; --O_VIDEO_B <= VideoB; VideoR <= O_VIDEO_R[0] & O_VIDEO_R[1] & O_VIDEO_R[2]; VideoG <= O_VIDEO_G[0] & O_VIDEO_G[1] & O_VIDEO_G[2]; VideoB <= O_VIDEO_B[0] & O_VIDEO_B[1];but still get this error ERROR:HDLCompiler:806 - "C:\vga7seg\source\seven_segment_top.vhd" Line 46: Syntax error near "0".ERROR:HDLCompiler:806 - "C:\vga7seg\source\seven_segment_top.vhd" Line 47: Syntax error near "0".ERROR:HDLCompiler:806 - "C:\vga7seg\source\seven_segment_top.vhd" Line 48: Syntax error near "0".ERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 98: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 99: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 100: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 101: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 102: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 103: Indexed name is not a std_logic_vectorERROR:HDLCompiler:854 - "C:\vga7seg\source\seven_segment_top.vhd" Line 23: Unit <rtl> ignored due to previous errorsalso I try to rewrite the line in difference way begin -- connect internal video signals to outputs --O_VIDEO_R <= VideoR; --O_VIDEO_G <= VideoG; --O_VIDEO_B <= VideoB; O_VIDEO_R <= VideoR[0] & VideoR[1] & VideoR[2]; O_VIDEO_G <= VideoG[0] & VideoG[1] & VideoG[2]; O_VIDEO_B <= VideoB[0] & VideoB[1];and still get this error ERROR:HDLCompiler:806 - "C:\vga7seg\source\seven_segment_top.vhd" Line 50: Syntax error near "0".ERROR:HDLCompiler:806 - "C:\vga7seg\source\seven_segment_top.vhd" Line 51: Syntax error near "0".ERROR:HDLCompiler:806 - "C:\vga7seg\source\seven_segment_top.vhd" Line 52: Syntax error near "0".ERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 97: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 98: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 99: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 100: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 101: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 102: Indexed name is not a std_logic_vectorERROR:HDLCompiler:854 - "C:\vga7seg\source\seven_segment_top.vhd" Line 23: Unit <rtl> ignored due to previous errors.
  10. Thanks for explain , Now I see this much complicated than what I expect, I have Intro to Spartan FPGA eBook about FPGA, I print it on A4 paper and read 3 or 4 paper in home or work when I have time but till now I didn't done 15% of the book so I thing I'm still newbile to understand your answer, it's really different when someone move from MCU to FPGA but I'll continue try. Thanks for helping Jaxartes.
  11. thank, I believe your answer solve my problem but I'm newbie in FPGA and I use it for do very simple example in my home like connect button and try to implement some gate when the board receive signal the led turn on and something like this, my problem is I don't know how to "make small changes to the syntax of the VHDL code" and don't understand what is that mean "you should probably connect the single bit to the msb of the multibit and set the non-msbs to zero.", Al last thanks for helping I was thought it will be easy to write hello world by using FPGA connected to LCD via VGA.
  12. what about this error message NgdBuild:604 - logical block 'font_gen_unit/frame_buffer_unit' with type 'video_ram' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'video_ram' is not supported in target 'spartan6'.
  13. Hi, I'm trying to implement Virtual 7 Segment display on VGA VHDL code on Nexys 3 board this code implemented on Papilio One with Megawing Shield http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/logicstart-megawing/virtual-7-segment-display-on-vga-r37 I change the VGA pinout in UCF file but there is something I don't understand it that Nexys 3 have 8 pins for VGA adapter 3 for green 3 for red 2 for blue NET "rgb[7]" LOC = U7 | IOSTANDARD = LVCMOS33;NET "rgb[6]" LOC = V7 | IOSTANDARD = LVCMOS33;NET "rgb[5]" LOC = N7 | IOSTANDARD = LVCMOS33;NET "rgb[4]" LOC = P8 | IOSTANDARD = LVCMOS33;NET "rgb[3]" LOC = T6 | IOSTANDARD = LVCMOS33;NET "rgb[2]" LOC = V6 | IOSTANDARD = LVCMOS33;NET "rgb[1]" LOC = R7 | IOSTANDARD = LVCMOS33;NET "rgb[0]" LOC = T7 | IOSTANDARD = LVCMOS33;While in the "Virtual 7 Segment display on VGA VHDL code" the author use only 1 pin for each color, Also mega wing schematic have the same thing there are primary pins VGA adapter and secondary pins (3 pins for green and red while blue got 2 pins) I make some change in the code to make it work in Nexys 3 FPGA board like changing the Entity from STD_LOGIC to STD_LOGIC_VECTOR (2 downto 0) But I still get this error ERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 88: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 89: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 90: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 91: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 92: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\Uvga7seg\source\seven_segment_top.vhd" Line 93: Indexed name is not a std_logic_vectorERROR:HDLCompiler:854 - "C:\vga7seg\source\seven_segment_top.vhd" Line 23: Unit <rtl> ignored due to previous errors. vga7seg.zip
  14. Hi, last day I was interesting to implement VGA driver in FPGA using Papilio board there is a tutorial written by alvie about using ZPUINO to drive VGA LCD display, it's a great tutorial for newbie and beginner but it's like using Arduino with some line of c code to show hello world, I want something written in VHDL, by the way I find this one http://papilio.cc/index.php?n=Playground.VGAGenerator written by Kevin Lindsey after download the source code for Github, I try to implement the top module for VGA Text when I use Xilinx 14.5 when I open the vga_text.xise I got this message I choose Backup and Migrate When I try to implement the top module I got this error Why this error show to me also I want to ask some question about this source code because I want to understand the fundamentals of how it’s work Q1/ I understand this file like font library for the character used to show on display font_unit - font_rom - arch (font_rom.vhd) as example -- code x32 "00000000", -- 0 "00000000", -- 1 "01111100", -- 2 ***** "11000110", -- 3 ** ** "00000110", -- 4 ** "00001100", -- 5 ** "00011000", -- 6 ** "00110000", -- 7 ** "01100000", -- 8 ** "11000000", -- 9 ** "11000110", -- a ** ** "11111110", -- b ******* "00000000", -- c "00000000", -- d "00000000", -- e "00000000", -- f This code used to print 2 on screen but how to call it I mean the way to print number 2 by call “code x32” or what ? Can someone explain to me how to print hello world by using this code on screen and how to change its location or color
  15. hmmm.. there is many newbie in this form want to learn how things works (not every thing just about FPGA) and I'm the first newbie . i think there is some peoples in this forum have the experience in PCB design and electronic Chip, i wish they give us some answers about my questions.