ohohnick

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  1. Hi Alvie! Just now I implemented it finally. Thanks so much for your time, suggestion and guide. Now I really know more about Wishbone and ZPUino. Thx! I appreciate!
  2. I will use the PS2 PORT on Arcade MegaWing to connect with the mouse. These two codes are from the ucf file which contains both the papilio pro and arcade megawing. NET ps2d LOC="P88" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # A12NET ps2c LOC="P93" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # A13 how to write these in the ZPUino top file in VHDL? Or I just need to modify the existing ucf file with ZPUino Vanilla for Papilio Pro?
  3. In the first pic attached, the problem is with the gpio_spp_read (1) & (2) signals, I guess there is nothing wrong with gpio_spp_data signals.
  4. hi Alvie New errors show up like this. Actually ps2c and ps2d are inout signals and I'm not sure how to connect these inout signals with GPIO.
  5. hi alvie more errors happen like this...
  6. ah... yes. But in which part I can add these codes? Or any part in the ZPUino top?
  7. And here is the Verilog codes for the mouse.v
  8. Thx for your reply Alvie. I really lack of knowledge in VHDL... here is the codes of the "zpuino_mouse_test". I just named it with a test but I actually connect the input and output signals of the mouse with the signals of the Wishbone.
  9. Hi there! I'm trying to add a new mouse module into ZPUino and I followed these steps: (in the ZPUino top level) 1. signal part signal mouse_ps2dz: std_ulogic; signal mouse_ps2cz: std_ulogic; 2. wishbone part slot8: zpuino_mouse_test port map ( wb_clk_i => wb_clk_i, wb_rst_i => wb_rst_i, wb_dat_o => slot_read(8), wb_adr_i => slot_address(8), wb_cyc_i => slot_cyc(8), wb_stb_i => slot_stb(8), wb_ack_o => slot_ack(8), wb_inta_o => slot_interrupt(8), ps2dz => mouse_ps2dz, ps2cz => mouse_ps2cz ); 3. pps part gpio_spp_data(6) <= mouse_ps2dz; gpio_spp_data(7) <= mouse_ps2cz; mouse_ps2dz <= gpio_spp_read(1); mouse_ps2cz <= gpio_spp_read(2); Because the ps2dz and ps2cz are inout signals But there is always an error : this line slot8: zpuino_mouse_test is not declared. I already added the file zpuino_mouse_test into the whole project and I can see it takes the place of "slot 8 empty device" I don't know why there is an error like this. I will be so grateful if there are some advice. Many thx!
  10. Hi Alvie Thx for your reply. Sorry I was busy with other parts of my project these days. I know more about the mouse module now. The PS2 mouse has the signals as x-axis(right/left) and y-axis(up/down) movement and the click statue of left, right and middle button. So the signals xm and ym are two 9-bit x-axis and y-axis movement signals and btm is a 3 bit button status signal. m_done_tick is a one-clock-cycle statue and is asserted when the assembled data is available. ps2d and ps2c are signals connecting with the mouse's transmitting and receiving system. I have checked all the VHDL files in the papilio_pro_lx9_vanilla_ise ZPUino. I think I can use one "empty device" such as "slot8" to implement the mouse. But I'm not sure what other files do I need to modify also.
  11. Thanks for your reply Alvie. btnm, xm, ym and tick are signals to control LEDs, when users move the PS2 mouse, the LEDs will light and react with different orders
  12. Hi there! I'm doing a project about insert a PS2 mouse created by Verilog into the ZPUino. I have run into some problems. 1. the PS2 mouse has two inputs: clock, reset, two inouts: ps2d, ps2c which are connected to the actual mouse, and four outputs: xm, ym, btnm, tick which connects to the wb_dat_o. I'm not sure what other wishbone signals I need to use in this module. 2. After connecting the mouse with wishbone, I need to insert it with ZPUino. And I don't know where to start.