jancumps

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About jancumps

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  1. I'm going to try this out. I have a stepper motor from a flatbed scanner, and a double h-bridge. The driver from seeed with the TI chip works different (the driver I'm using is featuring a dual H-Bridge, so that'll be simpler to control from the fpga). The experiment has to wait a bit, because my stepper and driver first have to feature in a contest that I'm participating in.
  2. wrong update
  3. I can confirm that the original reported problem is resolved by setting the following variable: LC_NUMERIC=en_US.UTF-8 In my profile this was set to nl_BE.UTF-8(because I'm from Belgium and my language is dutch, so that makes some sense ) I did this as a permanent setting by changing my $HOME/.pam_environment file, and loging out and in to linux again. Results in ISE when adding a Single ROM memory component: Generating ASY schematic symbol...INFO:sim:949 - Finished generation of ASY schematic symbol....Wrote CGP file for project 'memory'.Core Generator create command completed successfully.INFO:HDLCompiler:1061 - Parsing VHDL file "/home/jan/papilio/memorytest/ipcore_dir/memory.vhd" into library workINFO:ProjectMgmt - Parsing design hierarchy completed successfully.
  4. (I understand that this is an older topic) Because I ran into the same ASY file generation error as the original issue reported by Thomas, and because I'm running ISE on linux too, I searched for more info. Xylinx has accepted this as a known issue related to linux for non-US environments, and explain how you can set the environment to make it work. I'm going to try if I can fix it just by setting my decimal separator to dot in stead of comma...
  5. I have seen this board while troubleshooting my build of the IOBuffer - I have been thinking about going for the NPX/Philips IC for my implementation, but landed with the TI one (and that works fine). Inspired by the Pipistrello wing, I might change the constraint file of the Pro project you loaded here to use the 'C wing' connector for 16-31 too in stead of the 'B wing'. In my PCB design for the buffer I did not place the wing headers exactly on the board edge, so I can't plug one into 'A' and one into 'B'.
  6. I'm using (my own implementation of) an IOBuffer wing to get the Papilio 5v tolerant.
  7. Bit file for the Papillio Pro with pulldowns disabled,based on Magnus' project Logic_Sniffer.bit And the constraints file PapilioPro.ucf.tar.gz
  8. I've rebuild and tested an i2c circuit with and without pulldowns: (tested by altering A0 and A1 as follows): # indata[0-15] mapped to Wing A[0-15]NET "indata[0]" IOSTANDARD = LVCMOS33;....NET "indata[1]" IOSTANDARD = LVCMOS33;.....With pulldowns configured for A0 and A1: i2c signals approx 1 volt down NewFile1.bmp without pulldowns for A0 and A1: virtualy no impact on signal NewFile0.bmp
  9. Great, I'm going to do a diff with the code for the One to learn where the porting attempt is. I had these errors when switching your original code to X6, but was not sure how to handle that: ERROR:MapLib:30 - LOC constraint P4 on indata<23> is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P3 on indata<22> is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P91 on indata<16> is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P89 on bf_clock is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P86 on indata<15> is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P53 on indata<6> is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P18 on indata<0> is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P63 on extTriggerOut is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P90 on tx is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint P25 on armLEDnn is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.Diffing may give me a lead on how you do that. Eager to learn.
  10. Magnus, Do you have a version of the Pro port project source available? As a follow up on this thread , I'd like to check how to change the pulldown settings for the Pro. I haven't been successful in replicating your port to Pro starting from the source code you refered to here .
  11. I have used the raw bitfile for the Papillio Pro that was posted here on the forum, in thread http://forum.gadgetfactory.net/index.php?/topic/1925-porting-logic-analyser-from-one-to-pro/page-2#entry13904 I used them unchanged, just uploaded the file to the flash of my Pro According to mkarlsson they are based on the sources below: http://forum.gadgetfactory.net/index.php?/topic/1720-demon-307-ported-to-p1-250-500/#entry11322 I have not been able to replicate mkarlsson's work to regenerate for the Pro from source, I'm too novice for that at the moment. So I'm not yet able to change the pulldown settings.
  12. I have made a video on that a while ago.
  13. You can actualy turn your Papilio Pro itself into a logic analyzer. I'm using the buffer (the IO version, not the Input only version) together with the Papilio Pro and the OpenLogic Sniffer software as my analyzer.
  14. I'm happy with the OLS client. I got interested in sigrok when I saw what dreamsourcelab.com made of it (http://www.dreamsourcelab.com/dslogic.html). I tried buiding it from source. It worked, but I couldn't get the sniffer support working (see above). I'll check Magnus' comments and try to build with the latest sigrok release sources and the libraries from Magnus' github repository...