TomKeddie

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About TomKeddie

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  1. I made a batch of these a few years back, assembled one, can't use the rest. $US3 each on Tindie. https://www.tindie.com/products/TomKeddie/papilio-platform-logicstart-megawing-pcb-only/ Note these don't really suit the Duo, they're great for the Pro and One.
  2. tobia, I feel guilty that I never have found time to use the wing hamster sent me. if you do invest in a s6 let me know and I'll send the prototype on to you. Cheers, Tom
  3. Oops forgot about the first thing. @aliveboy @Filip @nilrods https://parallella.org/forums/viewtopic.php?f=11&t=3081
  4. Building a board for something like this is crazy. It is such a short lived product. You'd be much better off with a xilinx ultrascale or altera stratix V eval board for $5k. All the electonics is done, your value is surely in the algorithms. Anyway HFT is an immoral crock imho, that's all the help you'll get from me. Sharemarkets were created for companies to gain investment and share risk. hft benefits only a small few at the expense of society.
  5. Felix, I did sick of beige cases in openscad recently, take look at https://github.com/TomKeddie/openscad-scripts/tree/master/sick-of-beige Can also try to help you. Cheers, Tom
  6. Yes, will do. It will be some time before it will be really ready. Once I get home in a few weeks I'll put what I have on tindie and offer it to you guys first.
  7. Nice one thanks! Perhaps add a photo of the finished thing to the thingiverse listing? I am loving openscad more every day.....
  8. In my experience Xilinx does most of their development on linux these days, but they use centos. At work we have had trouble in the past getting xilinx to reproduce windows bugs due to the lack of developers using windows. This might apply to the newer vivado and not the ise we need for papilio. I recently managed to get one of their jtag cables working under linux, was surprised how easy that was.
  9. Yeah, I have one of each, Since only two are used I plan to remove two from one and place them on the other board. The connectors you are missing are a little cheaper and stocked by digikey. For some reason they only stock one side so I had to buy the ones I bought somewhere random like avnet for more money and expensive shipping.
  10. Will sell them close to cost (pcbs are $25 for 10), so probably $3 each plus postage. I also have some spare connectors - I bought 10, plan to sell 6 to recover the cost of the 10 - need 2 per board. I think it works out to about $8 each unfortunately, they suck so much. I need to prove the design some more, I did v1.0 late last year but family stuff has slowed v1.1 until now. I've proved the leds, xilinx jtag and usb serial on v1.0 - the i2c and buttons are a no show due to dumb schematic errors. Cheers, Tom
  11. While we're off topic, I've been quietly working on an i/o board for the parallela. Those samtec connectors suck (expensive and hard to buy) so much but I couldn't help myself. Feature list is - usb to serial ftdi chip - 8 leds - 4 buttons - lcd interface - level converters on all i/o - arduino style expansion connector - i2c wired out to arduino - fan connector - xilinx jtag connector (2mm) - arm jtag connector (2.54mm) - userled (from core, the rest of the i/o is fabric) I doubt there is any market for this but I will likely sell boards to cover the proto costs. I just sent rev 1.1 off. Images attached.
  12. You can script the control of the programming cable in TCL, lots of the bitcoin miners do this as io.
  13. Mike, I would skip the politics and push on with your content. You're a smart guy with lots of good stuff to share. Make it interesting and technical - they will come. I would love to explore the devicetree stuff more, soft peripherals etc this would attract the linux crowd. To me backbone of oshw has to be teaching interesting stuff for free. If the tools are free then you're in a better place that most of history. Even if the tools were open source the silicon is proprietary, like you say, we can't build our own chips in a foundry (this includes cpus that open software run onto). Cheers, Tom
  14. The serial is async, the usb just tunnels the chars from the software driver and outputs them async. In the fpga need a uart, I used the kcuart from Ken Chapman in my xilinx work, seemed to work well for me. There are a lot of crappy implementations I found that make assumptions about the incoming signal. Google "ken chapman kcuart" I think link 4 is a zip file. i think you need to provided a divided clock to set the baud rate. Cheers, Tom
  15. I just haven't had time to follow this project. I guess you're using the gtp transceivers? At work we use the xilinx ibert core to qualify the signal integrity. I've only used it on gtx and gth not sure about gtp or if it requires an expensive licence. perhaps i can build you a core but perhaps it is runtime licensed.